Event Scheduled for Jan 23, 2012
Event: ECE Seminar 'Energy Efficient Flow Control For On-Chip Networks and Future Directions' Georgios Michelogiannakis, Stanford University
Location: ITEB 336-Reception begins at 9:30 am
Time: 10:00 am
Details of Event:
With the advent of large-scale systems in a single die enabled by semiconductor technology scaling, on-chip networks have been developed to address the communication requirements of such systems. Past work has attributed as much as 40% of the chip power to the network, and as much as 22% of the network power to the buffers. This has motivated research on bufferless flow control to mitigate buffer overhead. In the first part of this talk, Mr. Michelogiannakis will present a comprehensive evaluation of bufferless flow control, highlighting various shortcomings at the network and system level. This discussion will show that bufferless networks offer marginal energy gains at best, compared to an optimized buffered network. In the second part of this talk, he will present elastic buffer flow control which uses pipeline flip-flops in the channels for buffering in lieu of input buffers. Therefore, the network retains storage without the overhead for input buffers. Elastic buffer flow control significantly simplifies router design and provides up to 43% more throughput per unit power as well as up to 45% shorter cycle time. In the last part of this talk Mr. Michelogiannakis will focus on future research directions and opportunities in on-chip networks.
George Michelogiannakis is currently completing his PhD studies at Stanford University. His research focus includes on-chip networks, specifically energy-efficient flow control. After publishing a comprehensive study on bufferless flow control, he proposed elastic buffer flow control to address the shortcomings of bufferless flow control and still mitigate buffering overhead. During this time, he also performed a study on hierarchical design of on-chip networks for large-scale chip multiprocessors. His latest work focuses on switch allocation in routers and improves allocation quality without extending cycle time. George Michelogiannakis is a recipient of a Stanford Graduate Fellowship and has
numerous publications in top-tier conferences and journals.
Target Audience: Open to All
Sponsored By: Electrical and Computer Engineering
No Pamphlet/Flyer Available