Selected publications

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Journal papers:

• X. Guan and Y. Fei, “Register file partitioning and re-compilation for register file power reduction,” accepted for publication in ACM Trans. on Design Automation of Electronic Systems.
• T. Hu and Y. Fei, “QELAR: A machine-learning-based adaptive routing protocol for energy efficient and lifetime-extended underwater sensor networks,” accepted for publication in IEEE Trans. on Mobile Computing.
• H. Lin, Y. Fei, X. Guan, and Z. J. Shi, “Architectural enhancement and system software support for program code integrity monitoring in application-specific instruction set processors,” accepted for publication in IEEE Trans. on VLSI.
• X. Guan and Y. Fei, “Register file partitioning and compiler support for reducing power consumption in embedded processors,” accepted for publication in IEEE Trans. on VLSI.
• H. Lin and Y. Fei, “Orchestrating horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” IEEE Trans. on Computers, vol. 58, no. 9, pp. 1211-1220, Sept. 2009.
• Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for dynamic software management in mobile computing systems,” ACM Trans. on Embedded Computing Systems, vol. 7, no. 3, Apr. 2008.
• Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for operating system driven embedded software,” ACM Trans. on Embedded Computing Systems, vol. 7, no. 1, Dec. 2007.
• Y. Fei and N. K. Jha, “Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip,” invited paper, Special Issue on Hardware-software Codesign for SOC in Int. Journal Embedded Systems, Vol.1, Nos.1/2, pp.2-13, 2005 (PDF).
• J. Luo, L. Zhong, Y. Fei, and N. K. Jha, “Register binding based RTL power management for control-flow intensive designs,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 23, no. 8, Aug. 2004. (PDF)
• Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “A hybrid energy estimation technique for extensible processors,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 652-664, May 2004. (PDF)
• Y. Fei, X. Zheng, H. Zhang, Y. Guo, and B. Zhou, “A novel scheme of power equalization and power management in WDM all-optical networks,” IEEE Photon. Technol. Lett., vol. 11, no. 9, pp.1189-1191, Sept.1999. (PDF)

Conferences and Workshops papers:

• J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.
• H. Lin and Y. Fei, “Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2009.
• X. Guan, Y. Fei, and H. Lin, “A hierarchical design of application-specific instruction set processors for high-throughput FFT,” in Proc. IEEE Int. Symp. on Circuits and Systems, May 2009.
• X. Guan, H. Lin, and Y. Fei, “Design of an application-specific instruction set processor for high-throughput and scalable FFT,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2009.
• H. Yan, Z. J. Shi, and Y. Fei, “Efficient implementation of Elliptic Curve Cryptography on DSP for underwater sensor networks,” WkShp on Optimizations for DSP & Embedded Systems (held in conjunction with IEEE/ACM Int. Symp. on Code Generation & Optimization), Mar. 2009.
• T. Hu and Y. Fei,  “QELAR - A Q-learning-based energy-efficient and lifetime-aware routing protocol for underwater sensor networks,” in IEEE Int. Performance Computing & Communications Conf., Dec. 2008.
• J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.
• V. Kundeti, Y. Fei, and Sanguthevar Rajasekaran, “An efficient digital circuit for implementing sequence alignment algorithm in an extended processor,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008.
• X. Guan and Y. Fei, “Reducing power consumption of embedded processors through register file partitioning and compiler support,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008. 
• H. Lin, G. Sun. Y. Fei, Y. Xie, and A. Sivasubramaniam, “Thermal-aware design considerations for application-specific instruction set processor,” in IEEE Symp. on Application Specific Processors, June, 2008.
• H. Lin and Y. Fei, “Harnessing horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” in Proc. IEEE Design Automation & Test in Europe Conf., Mar. 2008.
• H. Lin, X. Guan, Y. Fei, and Z. Shi, “Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors,” in IEEE Int. Conf. on Computer Design, Oct. 2007. (PDF)
• Y. Fei, H. D. Lin, and X. Guan, “A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors,” in IEEE Int. Midwest Symp. on Circuits & Systems, Aug. 2007.
• Y. Fei and Z. Shi, “Microarchitectural support for program code integrity monitoring in application-specific instruction set processors,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2007. (PDF)
• H.  Lin and Y. Fei, “Utilizing custom registers in application-specific instruction set processors for register spills elimination,” in Proc. ACM Great Lakes Symp. on VLSI, Mar. 2007. (PDF)
• Y. Fei and Z. Shi, “Embedding program code integrity monitoring in application-specific instruction set processors,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007.
• H. D. Lin and Y. Fei, “Custom register binding in application-specific instruction set processors to eliminate register spills,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007.
• Z. Shi and Y. Fei, “Exploring architectural challenges in scalable underwater wireless sensor networks,” in Annual Boston Area Computer Architecture Workshop (BARC), Feb., 2006.
• Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for coordinated dynamic software management in mobile computers,” in ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Oct. 2004. (PDF)
• Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for OS-driven embedded software,” in Proc. IEEE International Conference on VLSI Design, Jan. 2004. (PDF)
• W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong, A. Raghunathan, and N. K. Jha, “A comprehensive high-level synthesis system for control-flow intensive behaviors,” in Proc.IEEE Great Lakes Symposium on VLSI, April 2003. (PDF)

$$$   The behavioral synthesis tool for low power ASIC, namely IMPACT, is being commercialized by the company Alternative System  Concepts (ASC). Check out: http://www.ascinc.com/products/low_power/lowpowertool.html.

• Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy estimation for extensible processors,” in Proc. IEEE Design Automation & Test in Europe Conference, Mar. 2003. (PDF)
• L. Zhong, J. Luo, Y. Fei, and N. K. Jha, “Register binding based power management for high-level synthesis of control-flow intensive behaviors,” in Proc. IEEE Int. Conf. Computer Design, Sept. 2002. (PDF)
• Y. Fei and N. K. Jha, “Functional partitioning for low-power distributed systems of systems-on-a-chip,” in Proc. IEEE Asia South Pacific Design Automation Conference, Jan.2002. (PDF)