VLSI Design Verification and Testing


            ECE 6432: VLSI Design Verification and Testing, 3 Credits

            Time: Tue (3:30-6:00pm)

            Room: ITE 127



Dr. Mohammad Tehranipoor

Office: ITE 441

Phone: 860-486-3471

Email: tehrani at engr dot uconn dot edu

URL: http://www.engr.uconn.edu/~tehrani/teaching/index.html

Office hours: Tuesday 2-3pm or by appointment


            What VLSI Verification and Testing is about? 

Introduction to the concepts and techniques of VLSI (Very Large Scale Integration) design verification and testing, details of test economy, fault modeling and simulation, defects, Automatic Test Pattern Generation (ATPG), design for testability, Scan and Boundary scan architectures, built-in self-test (BIST) and current-based testing. Tools are used (in homeworks and projects) for ATPG, DFT, test synthesis and more. Students will use commercial DFT tools such as TetraMax, DFT Compiler and Analyzer, power analysis and management tools such as PrimePower and PowerMill from Synopsys. 

  Course Policy

  Tentative Course Outline


Why testing, Verification vs. Testing, Need for testing, Level of testing, Cost of testing, Roles of testing

  Test Process and Equipment

     Types of testing, Manufacturing test, Burn-in and stress test, Functional test, Automatic test equipment (ATE), Electrical parameter testing, DC parameter testing, AC parameter test

  Test Economics

     Basics of cost analysis, Benefit-cost analysis, Economics of design-for-testability (DFT), VLSI chip yield, Defect level

  Logic and Fault Modeling

     Logic modeling, Model types, Models at different levels of abstractions, Fault modeling, Common fault models, Stuck-at-faults, Transistor (switch) faults

  Fault Simulation

     Usage of fault simulators, Fault simulator in a VLSI design process, Fault simulation algorithms: Serial, Parallel, Deductive, Concurrent, Fault sampling

  Combinational ATPG (I)

     Structural vs. functional test, Definition of ATPG, Exhaustive algorithm, Random pattern generation, Boolean difference symbolic method, Path sensitization method, Computation complexity

  Combinational ATPG (II)

     Major ATPG algorithms, D-Algorithm, PODEM,

  ATPG Systems and Testability Measures

     ATPG systems, Static and dynamic compaction, Fault coverage and efficiency, Testability analysis, SCOAP measures, Controllability measure, Observability measure,

  Sequential Circuit ATPG

     Time frame expansion, Nine-valued logic, Drivability, Complexity of ATPG, Test generation system,

  Functional Testing

     Structure independent approach, Structure dependent approach, Microprocessor testing,

  Design-for-Testability (DFT) (I)

     Definition, Ad-hoc DFT methods, Scan design, Scan flip-flop, Muxed-DFF, LSSD, Scan test vectors, Multiple scan registers, Hierarchical scan,

  Design-for-Testability (DFT) (II)

     Partial scan architecture, Scan flip-flop selection methods, Cyclic and acyclic structures, Scan-hold flip-flops

  Delay Test

          Delay test problem, Path delay test, Transition Faults, Delay test methodologies, Test and diagnosis for Small-Delay Defects (SDDs)

  IDDQ Current Testing

     History and motivation, Basic principle of IDDQ testing, Fault detected by IDDQ tests, Limitations of IDDQ testing

  Memory Testing

     Motivation, Functional model of a memory, Fault models, March tests

  Built-In Self-Test (BIST) (I)

     Motivation, BIST definitions, BIST process, BIST pattern generation, BIST response compaction, Aliasing definition

  Built-In Self-Test (BIST) (II)

     Motivation, Built-in logic block observer, Test/clock systems, Test/scan systems, Test point insertion

  Low Power Test

     Motivation, Low power test, test power reduction techniques, ATPG based techniques, DFT based techniques, Low power BIST

  Boundary Scan

     Motivation, Bed-of-nails tester, Boundary scan hardware, JTAG standard (IEEE 1149.1), Elementary scan cell. Test access port (TAP) controller, Boundary scan instructions

  The Future of Testing - Research Opportunities





    M. Bushnell and V. Agrawal, Essentials of Electronic Testing, Kluwer Academic Publishers, 2000.

            Reference Material:

M. Abramovichi, M. Breuer and A. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1999.

L.T. Wang, C.W. Wu and X. Wen, VLSI Test Principles and Architectures, Elsevier, 2006.

            Course Evaluation:

  Participation, In-Class Exercise, Discussion      5%

  Homework Assignments/Project                     45%

  Exams                                                         50%




            Final Projects:

                Project Requirements and Deadlines


            Schedule for Talks and Discussion Session:



        ISCAS'85 and '89 Benchmarks

        ITC'99 Benchmarks    

        ITC'02 Benchmarks

        IWLS 2005 Benchmarks


            Useful Links:

         EE Times: SoC Testing Becomes a Challenge

         EE Times: Speakers Assess SoC Test Methods

         Prof. Krishnendu Chakrabarty, Duke University, Publications

         Agilent Technologies: SOC Test on the 93000 SOC Series

         Electronic Design: SoC Test System Speeds Design Verification, Cuts Test Cost

         Electronic Design: Standards Boost SoC Test

         Lucent Perspectives on SoC Testing

         EE Design: SoC test requirements debated

         Evaluation Engineering: SOC Designs Challenge, ATE Timing Architecture


         IEEE P1500 Standard for Embedded Core Test (SECT)


         Test Technology Technical Council (TTTC)

Related Conferences and Journals:


         International Test Conference (ITC)

         VLSI Test Symposum (VTS)

         Design Automation Conference (DAC)

         Design, Automation and Test in Europe (DATE)

         International Conference on Computer-Aided Design (ICCAD)

         International Conference on Computer Design (ICCD)

         Asian Test Symposium (ATS)

         Asia South Pacific DAC (ASP-DAC)


         IEEE Transactions on Computers

         IEEE Transactions on Computer-Aided Design

         IEEE Transactions on VLSI