VLSI Design Verification and Testing

            Course:

            ECE 300: VLSI Design Verification and Testing, Spring 2008, 3 Credits

            Time: Tu/Th (9:30-10:45am)

            Room: ITE 125

            Instructor: 

Dr. Mohammad Tehranipoor

Office: ITE 441

Phone: 860-486-3471

Email: tehrani at engr dot uconn dot edu

URL: http://www.engr.uconn.edu/~tehrani/teaching/index.html

Office hours: Tuesday 1-2pm or by appointment

            What VLSI Verification and Testing is about? 

Introduction to the concepts and techniques of VLSI (Very Large Scale Integration) design verification and testing, details of test economy, fault modeling and simulation, defects, Automatic Test Pattern Generation (ATPG), design for testability, Scan and Boundary scan architectures, built-in self-test (BIST) and current-based testing. Tools are used (in homeworks and projects) for ATPG, DFT, test synthesis and more. Students will use commercial DFT tools such as TetraMax, DFT Compiler and Analyzer, power analysis and management tools such as PrimePower and PowerMill from Synopsys. 

• Course Policy

• Tentative Course Outline

• Introduction

Why testing, Verification vs. Testing, Need for testing, Level of testing, Cost of testing, Roles of testing

• Test Process and Equipment

     Types of testing, Manufacturing test, Burn-in and stress test, Functional test, Automatic test equipment (ATE), Electrical parameter testing, DC parameter testing, AC parameter test

• Test Economics

     Basics of cost analysis, Benefit-cost analysis, Economics of design-for-testability (DFT), VLSI chip yield, Defect level

• Logic and Fault Modeling

     Logic modeling, Model types, Models at different levels of abstractions, Fault modeling, Common fault models, Stuck-at-faults, Transistor (switch) faults

• Fault Simulation

     Usage of fault simulators, Fault simulator in a VLSI design process, Fault simulation algorithms: Serial, Parallel, Deductive, Concurrent, Fault sampling

• Combinational ATPG (I)

     Structural vs. functional test, Definition of ATPG, Exhaustive algorithm, Random pattern generation, Boolean difference symbolic method, Path sensitization method, Computation complexity

• Combinational ATPG (II)

     Major ATPG algorithms, D-Algorithm, PODEM,

• ATPG Systems and Testability Measures

     ATPG systems, Static and dynamic compaction, Fault coverage and efficiency, Testability analysis, SCOAP measures, Controllability measure, Observability measure,

• Sequential Circuit ATPG

     Time frame expansion, Nine-valued logic, Drivability, Complexity of ATPG, Test generation system,

• Functional Testing

     Structure independent approach, Structure dependent approach, Microprocessor testing,

• Design-for-Testability (DFT) (I)

     Definition, Ad-hoc DFT methods, Scan design, Scan flip-flop, Muxed-DFF, LSSD, Scan test vectors, Multiple scan registers, Hierarchical scan,

• Design-for-Testability (DFT) (II)

     Partial scan architecture, Scan flip-flop selection methods, Cyclic and acyclic structures, Scan-hold flip-flops

• Delay Test

          Delay test problem, Path delay test, Transition Faults, Delay test methodologies

• I_DDQ Current Testing

     History and motivation, Basic principle of I_DDQ testing, Fault detected by I_DDQ tests, Limitations of I_DDQ testing

• Memory Testing

     Motivation, Functional model of a memory, Fault models, March tests

• Built-In Self-Test (BIST) (I)

     Motivation, BIST definitions, BIST process, BIST pattern generation, BIST response compaction, Aliasing definition

• Built-In Self-Test (BIST) (II)

     Motivation, Built-in logic block observer, Test/clock systems, Test/scan systems, Test point insertion

• Boundary Scan

     Motivation, Bed-of-nails tester, Boundary scan hardware, JTAG standard (IEEE 1149.1), Elementary scan cell. Test access port (TAP) controller, Boundary scan instructions