Invited Talks:
Invited Talk, IEEE Workshop on Design for Reliability and Variability (DRV), Oct. 2008
Invited Talk, IBM TJ Watson, Nov. 2008, Host: Dr. Jinjun Xiong
Invited Talk, Intel, Nov. 2008
Invited Talk, Fukuoka Industry, Science & Technology Foundation (FIST), Japan, Nov. 2008
IBM, Aug. 2008, Invited by: Dr. Phil Nigh
Magma, April 2008, Host: Dr. Sandeep Goel
Invited Speaker, SRC e-Workshop, Feb. 2008, Title: High-Quality Delay Tests for Nanotechnology Designs
Freescale, Austin, TX, Dec. 2007, Host: Dr. Magdy Abadir/Dr. Raj Raina
Texas Instruments, Dallas, TX, Dec. 2007, Hosts: Vinay Jayaram / Dr. Ken Butler
TranSwitch, Bedford, MA, Nov. 2007, Host: Zahi Abuhamdeh
AMD, Boston, MA, Nov. 2007, Host: Dr. Kamran Zarrineh
Analog Devices, Boston, MA, Nov. 2007, Host: Harry Chen
Guest Speaker, Magma's Luncheon Event at International Test Conference (ITC), San Jose, CA, Tuesday Oct. 23, 2007
Cadence, June 2007, Title: IR-drop Tolerant AT-speed Tests for Nanometer Technology Designs, Host: Dr. Krishna Chakravadhanula
LSI Logic, June 2007, Title: Generating High Quality At-speed Tests for Nanometer Technology Designs: Challenges and Solutions, Invited by: Dr. Sreejit Chakravarty
Qualcomm (San Diego, CA), June 2007, Title: At-speed Test for Nanotechnology: Challenges and Solutions, Host: Dr. Sagar Sabade
Guest Lecturer for VLSI System Testing Course of ECE Department at Duke University, Instructor: Prof. Krish Chakrabarty
Mentor Graphics (Wilsonville, OR), Nov. 2006, Title: At-speed Test for Nanotechnology: Challenges and Solutions, Host: Dr. Nilanjan Mukherjee
LSI Logic (San Jose, CA), Nov. 2006, Title: High Quality At-speed Tests for Nanotechnology Designs, Host: Dr. Arun Gunda
AMD (Sunnyvale, CA), Oct. 2006, Title: High Quality At-speed Tests for Nanometer High-speed Designs, Host: Dr. Anuja Sehgal
Texas Instruments (Dallas, TX), April 2004, Title: Enhanced Scan Architectures for Reducing Power and Test Application Time
Tutorials:
Tutorial, Aug. 12, 2008, MWSCAS, Title: High-Quality Delay Tests for Nanometer Technology Designs
Selected Presentations:
Int. Symposium on Defect and Fault Tolerance (DFT), Oct. 2008
Title:Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis
Int. Workshop on Hardware-Oriented and Security (HOST), June 2008
Title: Detection of Malicious Inclusions in Secure Hardware: Challenges and Solutions
Design, Automation & Test in Europe (DATE), March 2008
Title: Layout-Aware, IR-Drop Tolerant Transition-Delay Fault Pattern Generation
Design Automation Conference (DAC), 2007
Title: Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
SRC Annual Grant Review, 2007, Duke University, NC, Title: At-speed Transition Delay Test Using Low-Cost Testers
IEEE North Atlantic Test Workshop (NATW), 2007, Boxborough, MA, Title: IR-drop Tolerant Transition Delay Fault Testing in SOC Designs
ICCAD, Oct. 2006, Title: A Novel Framework for Faster-than-at-Speed Test Considering IR-drop Effects
DBT 2006, Title: Improving ATPG and Pattern Generation Selection for Screening Small Delay Defects
SRC Annual Grant Review, 2006, UCSB, CA, Title: At-speed Transition Delay Test Using Low-Cost Testers
Design Automation Conference (DAC), 2006
Title: A Hybrid FPGA Using Nanoscale Cluster and CMOS Scale Routing
Title: Timing-Based Delay Test for Screening Small Delay Defects
IEEE VLSI Test Symposium (VTS), Elevator Talk, 2006, Title: IR-Drop Effects on Faster-than-at-speed Delay Test
IEEE North Atlantic Test Workshop (NATW), 2005, Title: At-Speed Transition Fault Testing Using Low Speed Testers with Application to Reduced Scan Enable Routing Area
IEEE VLSI Test Symposium (VTS), 2005: Title: At-Speed Transition Fault Testing With Low Speed Scan Enable
Midwest Symposium on Circuits and Systems (MWSCAS), 2005
Title: Architecture of an Embedded Queue Management Engine for High-Speed Network Devices
Title: NnSP: Embedded Neural Networks Stream Processor
University of Maryland, Baltimore County (UMBC), 2004, Title: Nine-Coded Compression Technique for Reducing Test Application Time
University of Texas at Dallas, Center for Integrated Circuits and Systems (CICS), 2003, Title: Low-Power Test Pattern Generation Techniques
Midwest Symposium on Circuits and Systems (MWSCAS), 2002
Title: Test Optimization of Bus-Structured SoCs Using Embedded Microprocessor
Title: Fast Prototyping of a DSP Core