Publications

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Books

  1. M. Tehranipoor,  Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability, Springer, Target Publication Date: Nov. 23, 2007.

  2. M. Tehranipoor and N. Ahmed, Nanometer Technology Designs: High-Quality Delay Tests, Springer, Target Publication Date: Nov. 2007.

Book Chapters

  1. M. Tehranipoor,  “Test and Defect Tolerance for Nanoscale Crossbar-based Circuits,” in System on Chip Test Architectures: Nanometer Design for Testability, by L.T. Wang, Charles Stroud and Nur Touba, Elsevier, Target Publication Date: Oct. 2007.

  2. M. Tehranipoor and R. Rad, “Defect Tolerance for Reconfigurable Nanoscale Architectures,” in Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability, by Mohammad Tehranipoor, Springer, 2007.

Guest Editorials

  1. M. Tehranipoor and K. Butler, “IR-Drop and Power Supply Noise Effects on Design and Test of Very Deep Submicron Designs,” Guest Editorial, IEEE Design and Test of Computers, July 2007.

  2. M. Tehranipoor, “Test, Defect Tolerance and Reliability of Nanoscale Devices,” Guest Editorial, Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 23, No. 2/3, pp. 115-116, June 2007.

Journal Papers

  1. J. Lee and M. Tehranipoor, “Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity,” to appear in Journal of Low Power Electronics (JOLPE), 2009.

  2. M. Tehranipoor and R. Rad, “Defect Tolerance for Nanoscale Crossbar-based Devices,” to appear in IEEE Design & Test of Computers, 2008.

  3. R. Rad and M. Tehranipoor, “SCT: A Novel Approach For Testing and Configuring Nanoscale Devices,” to appear in ACM Journal on Emerging Technologies in Computing Systems (JETC), 2008.

  4. M. Nourani, M. Tehranipoor and N. Ahmed,  “Low-Transition Test Pattern Generation for BIST-Based Applications,” IEEE Transactions on Computers, vol. 57, no. 3, pp. 303-315, March 2008.

  5. J. Lee, M. Tehranipoor, C. Patel and J. Plusquellic, “Securing Designs Against Scan-Based Side-Channel Attacks,” IEEE Transactions on Dependable and Secure Computing (TDSC), vol. 4, no. 4, Oct.-Dec. 2007. .

  6. R. Rad and M. Tehranipoor, “Evaluating Area and Performance of a Hybrid FPGA with Nanoscale Clusters and CMOS Routing,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 3, no. 3, Nov. 2007.

  7. M. ElShoukry and M. Tehranipoor and C.P. Ravikumar, “A Critical-Path Aware Partial Gating Approach for Test Power Reduction,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12 ,  Issue 2, April 2007.

  8. N. Ahmed, M. Tehranipoor, C.P. Ravikumar and K. Butler, “Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 26, no. 5, pp. 896-906, May 2007.

  9. M. Tehranipoor and R. M.P. Rad, “Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based NanoFabrics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 26, no. 5, 943-958, May 2007.

  10. N. Ahmed and M. Tehranipoor,  “Improving Quality of Transition Delay Test Using Hybrid Scan-Based Technique,” IEEE Design and Test of Computers, 2006.

  11. D. Acharyya, A. Singh, M. Tehranipoor, C. Patel and J. Plusquellic, “Quiescent Signal Analysis: a Multiple Supply Pad IDDQ Method,” IEEE Design and Test of Computers, vol. 23, no. 4, pp. 278-293, 2006.

  12. M. Tehranipoor, M. Nourani and K. Chakrabarty, “Nine-Coded Compression Technique for Testing Embedded Cores in SoCs,”  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 13, no. 6, pp. 719-731, June 2005.

  13. M. Nourani and M. H. Tehranipour, “RL-Huffman Encoding for Test Compression and Power Reduction in Scan Application,”  ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 10, no. 1, pp. 91-115, Jan. 2005.

  14. M. H. Tehranipour, N. Ahmed and M. Nourani, “Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 23, issue 5, pp. 800-811, May 2004.

  15. M. H. Tehranipour, S. M. Fakhraie, Z. Navabi and M. R. Movahedin, “A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 20, pp. 155-168, April 2004.

  16. M. H. Tehranipour, S. M. Fakhraie, M. Nourani, M. R. Movahedin and Z. Navabi, “Embedded Test for Processor and Memory Cores in System-on-Chips,” International Journal of Science and Technology, vol. 10, no. 4, pp. 486-494, Oct. 2003.

Refereed Conference Papers

  1. H. Furukawa, X. Wen, K. Miyase, Y. Yamoto, S. Kajihara, P. Girard, L.T. Wang, M. Tehranipoor, “CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Testing,” to appear in IEEE Asian Test Symposium (ATS), 2008.

  2. J. Ma, J. Lee, M. Tehranipoor, X. Wen, A. Crouch, “Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG,” to appear in Int. Workshop on Defect and Data Driven Testing (D3T), 2008.

  3. X. Wang, M. Tehranipoor, and R. Datta, “Path-RO: A Novel On-Chip Critical Path Delay Measurement Under Process Variations,” to appear in International Conference on Computer-Aided Design (ICCAD), Nov. 2008.

  4. R. Rad, X. Wang, J. Plusquellic, and M. Tehranipoor, “Taxonomy of Trojans and Methods of Detection for IC Trust,” to appear in International Conference on Computer-Aided Design (ICCAD), Nov. 2008.

  5. X. Wang, H. Salmani, M. Tehranipoor, and J. Plusquellic, “Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis,” to appear in International Symposium on Fault and Defect Tolerance in VLSI Systems (DFT), Oct. 2008.

  6. X. Wang, M. Tehranipoor, and R. Datta "Accurate On-Chip Path Delay Measurement," Texas Instruments Symposium on Test (TIST), Aug.  2008

  7. J. Lee and M. Tehranipoor, "A Novel Test Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths," to appear in IEEE International Test Conference (ITC), Oct. 2008.

  8. M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects," to appear in IEEE International Test Conference (ITC), Oct. 2008.

  9. J. Ma, J. Lee, and M. Tehranipoor, “Power Distribution Failure Analysis Using Transition-Delay Fault Pattern Generation,” Poster presentation at IEEE International Test Conference (ITC), Oct. 2008.

  10. X. Wang, M. Tehranipoor, and R. Datta "Path-RO: On-Chip Critical Path Delay Measurement Under Process Variations," IEEE North Atlantic Test Workshop (NATW), May 2008 (Received Best Paper Award).

  11. J. Ma, J. Lee, M. Tehranipoor, and A. Crouch "Test Pattern Generation for Open Defects in Power Distribution Networks," IEEE North Atlantic Test Workshop (NATW), May 2008.

  12. J. Lee, S. Narayan, and M. Tehranipoor, "Low-Power Transition-Delay Fault Pattern Generation," IEEE North Atlantic Test Workshop (NATW), May 2008 (Received Honorable Mention for Best Paper Award).

  13. X. Wang, M. Tehranipoor, and J. Plusquellic, “Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions,” IEEE Int. Hardware-Oriented Security and Trust (HOST), 2008.

  14. R. Rad, J. Plusquellic, and M. Tehranipoor, “Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals,” IEEE Int. Hardware-Oriented Security and Trust (HOST), 2008.

  15. J. Lee and M. Tehranipoor, “LS-TDF: Low Switching Transition Delay Fault Test Pattern Generation,” in Proc. IEEE VLSI Test Symposium (VTS), 2008.

  16. M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Test Grading and Pattern Selection for Small Delay Defects,” in Proc. IEEE VLSI Test Symposium (VTS), 2008.

  17. J. Lee, S. Narayan, M. Kapralos, and M. Tehranipoor, “Layout-aware, IR-drop Tolerant Transition Fault Pattern Generation,” in Proc. Design, Automation, and Test in Europe (DATE), 2008.

  18. J. Lee, K. Peng, and M. Tehranipoor, "Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths," Poster presentation, SRC TECHCON, Austin, TX, 2008.

  19. M. Yilmaz, K. Chakrabarty and M. Tehranipoor, “Test Pattern Grading for Small Delay Defects,” Int. Workshop on Defect-Based Testing (DBT’07), 2007.

  20. R. Helinski, J. Plusquellic and M. Tehranipoor, “Small Delay Defect Detection Using Self-Relative Timing Bounds,” Int. Workshop on Defect-Based Testing (DBT’07), 2007.

  21. J. Lee and M. Tehranipoor,  “Delay Fault Testing in Presence of Maximum Crosstalk,” 16th IEEE North Atlantic Test Workshop (NATW'07), Boxborough, MA, 2007.

  22. N. Ahmed, M. Tehranipoor and V. Jayaram, “IR-drop Tolerant Transition Delay Fault Testing,” 16th IEEE North Atlantic Test Workshop (NATW'07), Boxborough, MA, 2007.

  23. N. Ahmed, M. Tehranipoor and V. Jayaram, “Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design,” in Proc. Design Automation Conference (DAC’07), 2007.

  24. N. Ahmed, M. Tehranipoor and V. Jayaram, “Supply Voltage Noise Aware ATPG for Transition Delay Faults,” in Proc. IEEE VLSI Test Symposium (VTS'07), 2007.

  25. N. Ahmed and M. Tehranipoor, “Supply Voltage Noise Aware ATPG for Transition Delay Faults,” TECHCON, Austin, TX 2007.

  26. N. Ahmed, M. Tehranipoor and V. Jayaram, “Improving ATPG and Pattern Selection for Screening Small Delay Defects,” IEEE Int. Workshop on Current and Defect Based Testing (DBT'06), 2006.

  27. J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, “Multiple Supply Pad IDDQ_based Defect Detection Techniques Applied to Hardware Test Chips,” IEEE Int. Workshop on Current and Defect Based Testing (DBT'06), 2006.

  28. J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, “Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad IDDQs: Test Chip Results,” in Proc. International Symposium for Testing and Failure Analysis Conference (ISTFA'06), 2006.

  29. N. Ahmed, M. Tehranipoor and V. Jayaram, “A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects,” in Proc. Int. Conf. on Computer-Aided Design (ICCAD'06), 2006.

  30. R. M. Rad and M. Tehranipoor, “A Hybrid FPGA Using Nanoscale Cluster and CMOS Scale Routing,” in Proc. Design Automation Conference (DAC’06), 2006.

  31. N. Ahmed, M. Tehranipoor and V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” in Proc. Design Automation Conference (DAC’06), 2006 (Nominated for Best Paper Award).

  32. R. M. Rad and M. Tehranipoor, “A Reconfiguration-based Defect Tolerance Method for Nanosclae Devices,” in Proc. Int. Symposium on Defect and Fault Tolerance of VLSI Systems (DFT’06), 2006.

  33. R. M. Rad and M. Tehranipoor, “SCT: An Approach for Testing and Configuring Nanoscale Devices,” in Proc. IEEE VLSI Test Symposium (VTS’06), 2006.

  34. J. Lee, M. Tehranipoorand J. Plusquellic, “A Low-Cost Solution for Protecting IPs Against Side-Channel Scan-Based Attacks,” In Proc. IEEE VLSI Test Symposium (VTS’06), 2006.

  35. R. M. Rad and M. Tehranipoor, “Test Time and Defect Map Analysis of PLA and LUT-Based Nano-Architectures,” IEEE North Atlantic Test Workshop (NATW’06), 2006.

  36. N. Ahmed, M. Tehranipoor and V. Jayaram, “A Case Study of IR-Drop Effects During Faster-than-at-Speed Delay Test,” IEEE North Atlantic Test Workshop (NATW’06), 2006.

  37. J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, “Triangulating to a Defect's Physical Coordinates Using Multiple Supply Pad IDDQs: Test Chip Results,” IEEE North Atlantic Test Workshop (NATW’06), 2006.

  38. J. Lee, N. Ahmed, M. Tehranipoor, V. Jayaram and J. Plusquellic, “A Novel Framework for Functionally Untestable Transition Fault Avoidance during ATPG,” IEEE North Atlantic Test Workshop (NATW’06), 2006.

  39. R. M. P. Rad and M. Tehranipoor, “Fine-Grained Island Style Architecture for Molecular Electronic Devices,” International Symposium on Field-Programmable Gate Arrays (FPGA'06) (Poster), 2006.

  40. M. Tehranipoor and R. M. P. Rad, “Test and Recovery for Fine-Grained Nanoscale Architectures,” International Symposium on Field-Programmable Gate Arrays (FPGA'06) (Poster), 2006.

  41. M. ElShoukry, C.P. Ravikumar and M. Tehranipoor, “Partial Gating Optimization for Power Reduction During Test Application,” in Proc. IEEE 14th Asian Test Symposium (ATS'05), 2005.

  42. M. Tehranipoor, M. Nourani and N. Ahmed, “Low Transition LFSR for BIST-Based Applications,” in Proc. IEEE 14th Asian Test Symposium (ATS'05), 2005.

  43. C.P. Ravikumar, N. Ahmed and M. Tehranipoor, “Practicing Transition-Fault Testing with Physical-Design-Friendly Flows,” Texas Instruments India Technical Conference (TIITC’05), 2005.

  44. J. Lee, M. Tehranipoor, C. Patel and J. Plusquellic, “Securing Scan Design Using Lock & Key Technique,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.

  45. N. Ahmed and M. Tehranipoor, “Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.

  46. M. Tehranipoor, “Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005.

  47. M. Alisafaee, S. M. Fakhraie and M. Tehranipoor, “Architecture of an Embedded Queue Management Engine for High-Speed Network Devices,” in Proc. IEEE MidWest Symposium on Circuits and Systems (MWSCAS'05), Cincinnati, 2005.

  48. H. Esmaeilzadeh, F. Farzan, N. Shahidi, S. M. Fakhraie, C. Lucas and M. Tehranipoor, “NnSP: Embedded Neural Networks Stream Processor,” in Proc. IEEE MidWest Symposium on Circuits and Systems (MWSCAS'05), Cincinnati, 2005.

  49. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, “Addressing At-speed Fault   Coverage and Test Cost Issues Using Enhanced Launch-off-Capture,” Texas Instruments Symposium on Test (TIST'05), 2005.

  50. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, “At-Speed Local Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers,” Texas Instruments Symposium on Test (TIST'05), 2005 (Ranked 5th Among 89 Presentations).

  51. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, “Enhanced Launch-off-Capture Transition Fault Testing,” in Proc. IEEE International Test Conf. (ITC'05), 2005 (Ranked top ten).

  52. N. Ahmed, M. Tehranipoor, C.P. Ravikumar and J. Plusquellic, “At-Speed Transition Fault Testing Using Low Speed Testers With Application to Reduced Scan Enable Routing Area,” IEEE North Atlantic Test Workshop (NATW'05), pp. 112-119, 2005.

  53. D. Acharyya, A. singh, M. Tehranipoor, C. Patel and J. Plusquellic, “Sensitivity Analysis of Quiescent Signal Analysis for Defect Detection,” IEEE. Int. Workshop on Defect Based Testing (DBT'05), pp. 3-10, 2005.

  54. M. Nourani, M. Tehranipoor and N. Ahmed, “Pattern Generation and Estimation for Power Supply Noise Analysis,” in proc. IEEE VLSI Test Symposium (VTS'05), pp. 439-444, 2005.

  55. N. Ahmed, C.P. Ravikumar, M. Tehranipoor and J. Plusquellic, “At-Speed Transition Fault Testing With Low Speed Scan Enable,” in proc. IEEE VLSI Test Symposium (VTS'05), pp. 42-47, 2005 (Received Best Paper Award).

  56. M. H. Tehranipour, M. Nourani and K. Chakrabarty, “Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression,” in proc. IEEE/ACM Design, Automation and Test in Europe (DATE'04), Paris, France, vol. 2, pp. 1284-1289, 2004.

  57. M. H. Tehranipour, M. Nourani, K. Arabi and A. Afzali-Kusha, “Mixed RL-Huffman Encoding for Power Reduction and Data Compression in Scan Test,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’04), Vancouver, Canada, vol. 2, pp. 681-684, 2004.

  58. N. Ahmed, M. H. Tehranipour and M. Nourani, “Low-Power Pattern Generation for BIST Architecture,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’04), Vancouver, Canada, vol. 2, pp. 689-692, 2004.

  59. N. Ahmed, M. H. Tehranipour, D. Zhou and M. Nourani,, “Frequency Driven Repeater Insertion for Deep Submicron,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’04), Vancouver, Canada, vol. 5, 181-184, 2004.

  60. M. H. Tehranipour, N. Ahmed and M. Nourani, “Testing SoC Interconnects for Signal Integrity Using Boundary Scan,” in proc. IEEE VLSI Test Symposium (VTS'03), Napa, CA, pp. 158-163,  2003.

  61. N. Ahmed, M. H. Tehranipour and M. Nourani, “Extending JTAG for Testing Signal Integrity in SoCs,” in proc. IEEE/ACM Design, Automation and Test in Europe (DATE'03), Messe Munich, Germany, pp. 218-223, 2003.

  62. M. H. Tehranipour, N. Ahmed and M. Nourani, “Multiple Transition Model and Enhanced Boundary Scan Architecure to Test Interconnects for Signal Integrity,” in proc. IEEE International Conference on Computer Design (ICCD'03), San-Jose, pp. 554-559, CA, 2003.

  63. M. H. Tehranipour, M. Nourani and S. M. Fakhraie, “Systematic Test Program Generation for SoC Testing Using Embedded Processor,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS'03), Bangkok, Thailand, vol. 5, pp. 541-544, 2003.

  64. G. R. Chaji, R. M. Pourrrad, S. M. Fakhraie and M. H. Tehranipour, “eUTDSP: A Design Study of a New VLIW-Based DSP Architecture,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS'03), Bangkok, Thailand, vol. 4, pp. 137-140, 2003.

  65. M. H. Tehranipour and M. Nourani, “Signal Integrity Loss in SoC's Interconnects: A Diagnostic Approach Using Embedded Microprocessor,” in proc. IEEE International Test Conference (ITC'02), Baltimore, MD, pp.1093-1102, 2002.  

  66. S. M. Fakhraie, M. H. Tehranipour, M. R. Movahedin and M. Nourani, “Fast Prototyping of a DSP Core,” in proc. IEEE MidWest Symposium on Circuits and Systems (MWSCAS'02), Tulsa, Oklahoma, vol. 2, pp. 215-218, 2002.

  67. M. H. Tehranipour, M. Nourani, S. M. Fakhraie and C. A. Papachristou, “Test Optimization of Bus-Structured SoCs Using Embedded Microprocessor,” in proc. IEEE MidWest Symposium on Circuits and Systems (MWSCAS'02), Tulsa, Oklahoma, vol. 1, pp. 168-171, 2002.

  68. M. H. Tehranipour, Z. Navabi and S. M. Fakhraie, “An Efficient BIST for Embedded SRAM Testing,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS'01), Sydney, Australia, Vol 5, pp. 73-76, 2001. 

  69. M. H. Tehranipour, Z. Navabi and S. M. Fakhraie, “A Low-Cost BIST Architecture for Processor Cores,” in proc. IEEE Electronic Circuits and Systems Conference (ECS'01), Bratislava, Slovakia,  pp. 11-14, 2001.

  70. M. H. Tehranipour and Z. Navabi, “Zero-Overhead BIST for Internal SRAM Testing,” in proc. IEEE International Conference on Microelectronics (ICM'00), Tehran, Iran, pp. 109-112, 2000.

Technical Reports and Invited Poster Presentations

  1. J. Lee and M. Tehranipoor, "Low-power Transition Delay Fault Test Pattern Generation," IEEE VLSI Test Symposium (VTS), 2008, PhD Thesis Poster Presentation.

  2. M. Tehranipoor, "Trojan Detection and Isolation in Integrated Circuits," NSF Cyber Trust meeting, New Haven, March 2008

  3. N. Ahmed, M. Tehranipoor, and V. Jayaram, “Considering IR-Drop Effects During Faster-than-at-Speed Delay Test,” presented in Special Session (Elevator Talk), IEEE VLSI Test Symposium (VTS), 2006.

  4. N. Ahmed and M. Tehranipoor, “On-chip Scan Enable Generation for Transition Fault Testing,” Poster Presentation, University  Booth, ITC 2005.

  5. J. Plusquellic, D. Acharyya, C. Patel, A. Singh and M. Tehranipoor, “Hardware Investigation of Defect Sensitivity of a Multiple  Supply Pad IDDQ Method,” Poster Presentation, University Booth, ITC 2005.

  6. N. Ahmed and M. Tehranipoor, “Enhanced Launch-off-Capture with Improved Fault Coverage and Reduced Pattern Count,” Presented in UT-Austin Poster Session, ITC 2005.

  7. M. H. Tehranipour and M. Nourani, “Low-Power Test pattern generation for BIST Architecture,” University of Texas at Dallas, 2003.

  8. M. H. Tehranipour and M. Nourani, “Test Compression and Power Reduction in Scan Using RL-Huffman Encoding,” University of Texas at Dallas, 2002.