Professional Activities

Chair Position:

  • Program Chair, ARO Special Workshop on Hardware Assurance, UConn, August 2009

  • General Chair, IEEE Workshop on Defect and Data Driven Testing (D3T), 2009

  • General Chair, International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT), 2009

  • General Chair, IEEE International Workshop on Hardware-Oriented Security and Trust (HOST), 2009

  • Program Chair, IEEE Workshop on Defect and Data Driven Testing (D3T), 2008, Santa Clara, CA

  • Steering Committee Chair, IEEE International Workshop on Hardware-Oriented Security and Trust (HOST)

  • General Chair, 1st IEEE International Workshop on Hardware-Oriented Security and Trust (HOST), 2008

  • Program Chair, IEEE Workshop on Defect Based Testing (DBT), 2007, Santa Clara, CA

  • Co-Program Chair, International Symposium on Defect and Fault Tolerance of VLSI Systems (DFT), 2008, Boston, MA

  • Local Arrangement Chair, IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), 2006

Editor:

  • Associate Editor, IEEE Design & Test of Computers

  • Associate Editor, Journal of Electronic Testing: Theory and Applications (JETTA), 2007-present

  • Editor, TTTC News Letter

  • Guest Editor, Special issue on "Test, Defect Tolerance, and Reliability of Nanoscale Devices", Journal of Electronic Testing: Theory and Applications (JETTA)

  • Guest Editor, Special issue on "IR-Drop and power Supply Noise Effects on Design and Tetst of Very Deep Submicron Designs", IEEE Design & Test of Computers, Guest Co-editor: Ken Butler (Texas Instruments)

  • Guest Editor, IEEE Design & Test Special Issue on "Verifying Physical Trustworthiness of Integrated Circuits and Systems", Guest Editors: Mohammad Tehranipoor (UConn) and Farinaz Koushanfar (Rice University)

Panels:

  • Panel Organizer, Title: Zero Defect (Zero DPPM): How can we get there?,  Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2008

  • Panel Co-organizer, Title: Challenges in Test Data Collection and Analysis, Int. Workshop on  Defect and Data Driven Testing, (D3T), Oct. 2008

  • Panel Organizer, Title: Test and Diagnosis for Parametric Failures,  Int. Workshop on  Defect and Data Driven Testing, (D3T), Nov. 2009

  • Panelist, WRTLT, Sapporo, Japan, Nov. 2008.

  • Panelist, IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 2009

  • Panelist, International Test Conference (ITC), Nov. 2009, Austin, TX

  • Panel Co-organizer (with Kee Sup Kim from Intel), Title: Three Questions to Oracle (Data required for test engineers and researchers in academia), IEEE VLSI Test Symposium (VTS), 2006

  • Panel Co-organizer (with Hank Walker, Texas A&M University), Title: Process Variations + Systematic Defects: Can DBT Help? , International Workshop on Defect-Based Testing (DBT), 2007.

  • Proposal reviewer and panelist for the National Science Foundation (NSF), 2005, 2006, 2009

Memberships:

  • Senior Member, IEEE

  • Member, ACM, ACM SIGDA

  • Member, TTTC

  • Member, TTTC Middle East and Africa Group

Program Committees:

  • Design, Automation, and Test in Europe (DATE), 2009

  • IEEE VLSI Test Symposium (VTS), 2010

  • ACM SIGDA Ph.D. DAC Forum, 2008-present

  • IEEE Workshop on RTL and High Level Testing (WRTLT), 2009

  • ACM Great Lake Symposium on VLSI (GLSVLSI), 2008-present

  • International Conference on Communication Theory, Reliability, and Quality of Service (CTRQ), 2008-present

  • IEEE Int. Workshop on Defect Based Testing (DBT), 2005-present

  • Int. Conference on Computer Design (ICCD), 2008.

  • North Atlantic Test Workshop (NATW) 2004-present

  • IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT ), 2005, 2006, 2007

  • International Design and Test Workshop (IDT), 2006, 2007, 2008

  • International Symposium on Nanoscale Architectures (NanoArch), 2007, 2008, 2009

  • IEEE Int. On-Line Testing Symposium (IOLTS), 2009

  • Int. Workshop on Impact of Low-Power Design on Test and Reliability, 2009

  • Workshop on Unique Chips and Systems (UCAS), 2009

  • IEEE Workshop on Design for Reliability and Variability (DRV), 2009

Session Chair:

  • Int. Workshop on Current and Defect-Based Testing (DBT'05)

  • IEEE North Atlantic Test Workshop (NATW), 2006, 2007, 2008, 2009

  • International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06)

  • Design Automation Conference (DAC'07)

  • International Symposium on Nanoscale Architectures (NanoArch), 2008

  • International Test Conference (ITC), 2006, 2008, 2009

  • IEEE Workshop on RTL and High Level Testing (WRTLT'08)

Selected Review Activities:

  • National Science Foundation (NSF)

  • IEEE Transactions on Computer-Aided Design of of Integrated Circuits and Systems

  • IEEE Transactions on Very Large Scale Integration Systems

  • IEEE Transactions on Computers

  • ACM Transactions on Design Automation of Electronic Systems (TODAES)

  • Journal of Electronic Testing: Theory and Applications (JETTA)

  • ACM Journal on Emerging Technologies in Computing Systems (JETC)

  • Design, Automation, and Test in Europe (DATE)

  • IEEE Conference on VLSI

  • IEEE Workshop on RTL Test (ARTLT)

  • International Test Conference (ITC)

  • Great Lake Symposium on VLSI (GLSVLSI)

  • IBM Journal of Research and Development

  • IEEE North Atlantic Test Workshop (NATW)

  • IEEE Communication Magazine

  • IEEE VLSI Test Symposium (VTS)

  • International Conference on Microelectronics (ICM)

  • International Journal of Computers and Applications

  • IEEE Asian Test Symposium (ATS)

  • Design Automation Conference (DAC)