Shuo Wang 

Electrical & Computer Engineering
University of Connecticut

371 Fairfield Road U-2157

Storrs, CT 06269-2157, USA 
 

Tel:  860-486-4548

E-Mail: shuo.wang AT engr.uconn.edu
Office: BECAT A65

Shuo Wang received his B.Engr. and M.Engr. degrees from Beijing University of Aeronautics and Astronautics, China, in 2002 and 2005, respectively. Since August 2005, he has been working towards the Ph.D. degree in Department of Electrical and Computer Engineering, University of Connecticut, under the guidance of Prof. Lei Wang. His research focus is currently on architecture/microarchitecture level techniques for emerging challenges in nanoscale integrated systems.

Education

Journal Publications

  • S. Wang and L. Wang, "Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency," IEEE Transactions on VLSI Systems (TVLSI), accepted as a regular paper. (pdf)
  • S. Wang, L. Wang and F. Jain, "Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation," ACM Journal of Emerging Technologies in Computing (JETC), invited paper, to appear. (pdf)

Conference Publications

(In the area of computer engineering, premier conferences are usually at least as important as journals. Most conferences are fairly competitive with rigorous reviews and very low acceptance rate.)

  • S. Wang, F. Zhang, J. Dai, L. Wang, and Z. Shi, "Making register file resistant to power analysis attacks," International Conference on Computer Design (ICCD), 2008, accepted. (pdf, ppt)
  • S. Wang and L. Wang, "A defect-tolerant memory nanoarchitecture exploiting hybrid redundancy," IEEE International Conference on Nanotechnology (NANO), 2008, invited presentation paper. (pdf, ppt)
  • S. Wang, J. Dai, and L. Wang, "Digital filtering with unreliable molecular electronics," IEEE International Conference on Nanotechnology (NANO), 2008, accepted. (pdf, ppt)
  • S. Wang, J. Dai, and L. Wang, "Defect-Tolerant Digital Filtering with Unreliable Molecular Electronics," Workshop on Signal Processing Systems (SiPS), 2008, accepted. (pdf, ppt)
  • S. Wang and L. Wang, "Design of Error-Tolerant Cache Memory for Multithreaded Computing," International Symposium on Circuits and Systems (ISCAS), pp. 1850-1853, 2008. (pdf, ppt)
  • S. Wang, J. Dai, E.-S. Hasaneen, L. Wang, and F. Jain, "Programmable Threshold Voltage Using Quantum Dot Transistors for Low-Power Mobile Computing," International Symposium on Circuits and Systems (ISCAS), pp. 3350-3353, 2008. (pdf, ppt)
  • S. Wang and L. Wang, "Dynamic Redundancy Allocation for Reliable and High-Performance Nanocomputing," International Symposium on Nanoscale Architectures (NANOARCH), pp. 1-6, 2007. (pdf, ppt)
  • S. Wang, J. Dai, E.-S. Hasaneen, R. Shankar, R. Velampati, L. Wang, and F. Jain, "Low-Power CMOS using Programmable Threshold QD-FETs," Connecticut Microelectronics and Optoelectronics Consortium (CMOC), 2007. (pdf, ppt)
  • S. Wang and L. Wang, "Soft-redundancy allocated cache microarchitecture," Annual Boston Area Computer Architecture Workshop (BARC), pp. 43-48, 2007. (pdf, ppt)
  • S. Wang and L. Wang, "Exploiting soft redundancy for error-resilient on-chip memory design," International Conference on Computer-Aided Design (ICCAD), pp. 535-540, 2006. (pdf, ppt)
  • S. Wang and L. Wang, "Joint performance improvement and error tolerance for memory design based on soft indexing," International Conference on Computer Design (ICCD), pp. 25-30, 2006. (pdf, ppt)
  • S. Wang and L. Wang, "Thread-associative memory for multicore and multithreaded computing," International Symposium on Low Power Electronics and Design (ISLPED), pp. 139-142, 2006. (pdf, ppt)
  • L. Wang and S. Wang, "Adaptive timing for analysis of skew tolerance," International Symposium on Circuits and Systems (ISCAS), pp. 976-979, 2006. (pdf, ppt)