Office Hours: Tuesday 11am-Noon or by appointment via email
TA
Hamza Omar
Email: hamza.omar@uconn.edu
Office Hours: Monday 2:30-3:30pm in ITE 134, Wednesday 1:00-2:00pm in ITE 138, and Friday 2-2:30pm
Announcements
Final Exam -- May 3, 2018 (8AM -- 10AM in LH 205; Cumulative exam; topics)
Textbook: Digital Systems Design Using VHDL by Charles Roth and Lizy John, 3rd Edition
Labs: ECS Learning Center room in ITEB 134 (Mondays 2:30-3:30pm) and ITEB 138 (Wednesdays 1:00-2:00pm) reserved for help with labs. The TA will also make himself available if student(s) email him in advance to meet Friday from 2-2:30 in ITEB 134
Lectures
Lecture 1: Introduction to Logic Design and Hardware Descriptive Languages - PDF (textbook reading: 1.1 - 1.3)
Lecture 2: Combinatorial Logic and VHDL - PDF (textbook reading: 1.4 - 1.5 and 2.1 - 2.4) (VHDL example: cir1.vhd, cir1test.vhd)
Lecture 22: Design for Test and Security - PDF (no textbook reading)
Homeworks (due at start of class - no late submissions will be accepted)
Homework 1 (due Jan 30, 2018): problems 1.2, 1.5, 1.11, 2.3, 2.6a (you can download the homework problems and the solution here)
Homework 2 (due Feb 13, 2018): problems 2.8, 2.11, 2.22, 2.23, 2.15 (you can download the homework problems and the solution here)
Homework 3 (due Feb 22, 2018): problems 2.9, 2.24, 2.38a, 2.51 (you can download the homework problems and the solution here)
Homework 4 (due Mar 20, 2018): problems 1.14a, 1.18, 2.39b, 2.42 (you can download the homework problems and the solution here)
Homework 5 (due Mar 29, 2018): problems 5.2, 5.12b, 5.12d, 5.17, 5.24 (you can download the homework problems and the solution here)
Homework 6 (not graded): you can download the homework problems here
Homework 7 (due Apr 24, 2018): problems 3.10a, 3.12a (you can download the homework problems and the solution here)
Lab Assignments (due at start of class - no late submissions will be accepted)
NOTE: (1) Utilize the optional lab hours - Mondays 2:30-3:30pm in ITE 134 and Wednesdays 1:00-2:00pm in ITE 138, (2) Take a look at the VHDL Toolchain Guide PDF
Lab 0 (due Jan 25, 2018): Complete all steps for the toolchain setup and run the lab0 with test0 testbench. Submit your simulation output on a single page. Don't forget to write your name on your submission! Lab0 Guide PDF, lab0.vhd, test0.vhd