Office Hours: Friday 2-4pm in ITEB 138, Monday 2-3:30pm in ITEB 138/134 or appointment via email
Announcements
Final exam will be on 5/3/2017 (Wednesday) 6PM-8PM in LH 306. The final exam is commulative
No class on April 21st. Submit your Lab3 report to the TA in ITE 427 between 11AM-Noon on April 21st.
Exam 2 will be in class on April 7th, 2017. It will cover lectures 9 through 16
Exam 1 will be in class on March 3rd, 2017. It will cover Lectures 1 to 9. From lecture 9 it will only cover upto the end of discussion on counters (slides 1-12)
Textbook: Digital Systems Design Using VHDL by Charles Roth and Lizy John, 3rd Edition
Labs: ECS Learning Center room ITEB 138 has been reserved on Fridays from 2-4pm. Moreover, the TA will be available in ITEB 138/134 on Mondays from 2-3:30pm. Attending these sessions is not required. However, we have setup these slots for you to complete the labs and get help!
Lectures
Lecture 1: Introduction to Logic Design and Hardware Descriptive Languages - PDF (textbook reading: 1.1 - 1.3)
Lecture 2: Combinatorial Logic and VHDL - PDF (textbook reading: 1.4 - 1.5 and 2.1 - 2.4)
Lecture 21: Timing Synchronous Designs and Computer-Aided Design (CAD) - PDF (no textbook reading)
Lecture 22: Verification and Testing of Digital Systems - PDF (no textbook reading)
Homeworks (due at start of class - no late submissions will be accepted)
Homework 1 (due Feb 3, 2017): problems 1.1, 1.5, 1.6, 1.10, 2.3, 2.5a, 2.19, 2.26 (you can download the homework problems and the solution here)
Homework 2 (due Feb 17, 2017): problems 1.13, 2.7, 2.9, 2.10, 2.17, 2.18, 2.24b (you can download the homework problems and the solution here)
Homework 3 (due March 10, 2017 due March 24, 2017): problems 1.15a, 1.16a, 1.18, 1.22, 2.38a, 2.39, 2.43, 2.52 (you can download the homework problems and the solution here)
Homework 4 (due March 31, 2017): problems 5.1, 5.16-b-c, 5.17, 5.21-b-c (you can download the homework problems and the solution here)
Homework 5 (due April 28, 2017): problems 5.13, 5.24, 3.3, 3.11a, 3.12a, 3.14 (you can download the homework problems and the solution here)
Lab Assignments (due at start of class - no late submissions will be accepted)
NOTE: (1) Utilize the optional lab hours - Fridays 2-4pm in ITE 138 and Mondays 2-3:30pm in ITE 138/134, (2) Take a look at the VHDL Toolchain Guide PDF
Lab 0 (due Feb 3, 2017): Complete all steps for the toolchain setup and run the lab0 with test0 testbench. Submit your simulation output on a single page. Don't forget to write your name on your submission! Lab0 Guide PDF, lab0.vhd, test0.vhd