Selected publications
Journal articles:
- J. Dai, L. Wang, and F. Jain, "Analysis of defect tolerance in molecular crossbar electronics," IEEE Trans. on VLSI Systems, accepted.
- S. Wang and L. Wang, "Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency," IEEE Trans. on VLSI Systems, accepted.
- S. Wang and L. Wang, "Analysis of deskew signaling via adaptive timing," IEEE Trans. on CAD, accepted.
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- S. Wang, L. Wang, and F. Jain, "Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation," ACM Journal on Emerging Technologies in Computing Systems, accepted.
- L. Wang and N. Patel, "Improving error tolerance for multithreaded register files," IEEE Trans. on VLSI Systems, vol. 16, pp. 1009-1020, August 2008.
- L. Wang and N. Patel, "Low-complexity analysis of repetitive regularities for biometric applications," Journal of Computers, vol. 2, pp. 56-64, August 2007.
- L. Wang and N. R. Shanbhag, "Low-power MIMO signal processing," IEEE Trans. on VLSI Systems, vol. 11, pp. 434-445, June 2003.
- L. Wang and N. R. Shanbhag, "Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise,"IEEE Trans. on VLSI Systems, vol. 11, pp. 254-269, April 2003.
- L. Wang and N. R. Shanbhag, "Low-power filtering via adaptive error-cancellation," IEEE Trans. on Signal Processing, vol. 51, pp. 575-583, February 2003.
- L. Wang and N. R. Shanbhag, "An energy-efficient, noise-tolerant dynamic circuit technique," IEEE Trans. on Circuits and Systems, vol. 47, pp. 1300-1306, November 2000.
- S. Wang, J. Dai, E. Hasaneen, L. Wang, and F. Jain, "Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing," submitted to ACM Journal on Emerging Technologies in Computing Systems.
Conference papers:
- S. Wang, F. Zhang, J. Dai, L. Wang, and J. Shi, "Making register file resistant to power analysis attacks," IEEE International Conference on Computer Design, 2008, accepted.
- W. Tang and L. Wang, "Cooperative OFDM for energy-efficient wireless sensor networks," IEEE Workshop on Signal Processing Systems (SiPS), 2008, accepted.
- S. Wang, J. Dai, and L. Wang, "'Defect-tolerant digital filtering with unreliable molecular electronics'," IEEE Workshop on Signal Processing Systems (SiPS), 2008, accepted.
- Invited paper presentation: S. Wang and L. Wang, "A defect-tolerant memory nanoarchitecture exploiting hybrid redundancy," IEEE International Conference on Nanotechnology, 2008, pp. 707-710.
- S. Wang, J. Dai, and L. Wang, "Digital filtering with unreliable molecular electronics," IEEE International Conference on Nanotechnology, 2008, pp. 891-894.
- J. Dai, L. Wang, and F. Jain, "A quantitative approach for analysis of defect tolerance in QCA," IEEE International Conference on Nanotechnology, 2008, pp. 903-906.
- W. Tang and L. Wang, "Design of digital signal processing modules with nanoelectronics," IEEE International Conference on Nanotechnology, 2008, pp. 741-744
- W. Tang and L. Wang, "A DSP nanosystem with defect tolerance," Proc. IEEE/ACM Symposium on Nanoscale Architectures,, 2008, pp. 32-37.
- S. Wang and L. Wang, "Design of error-tolerant cache memory for multithreaded computing," Proc. of International Symposium on Circuits and Systems (ISCAS), 2008, pp. 1850-1853.
- S. Wang, J. Dai, E. Hasan, L. Wang, and F. Jain, "Programmable threshold voltage using quantum dot transistors for low-power mobile computing," Proc. of International Symposium on Circuits and Systems (ISCAS), 2008, pp. 3350-3353.
- S. Wang, L. Wang, and F. Jain, "Dynamic redundancy allocation for reliable and high-performance nanocomputing," Proc. of IEEE/ACM Symposium on Nanoscale Architectures,, 2007, pp. 1-6.
- J. Dai, L. Wang, and F. Jain, "Analysis of defect tolerance in molecular electronics using information-theoretic measures," Proc. of IEEE/ACM Symposium on Nanoscale Architectures, 2007, pp. 21-26.
- S. Wang and L. Wang, "Soft-redundancy allocated cache microarchitecture," Proc. of Annual Boston Area Computer Architecture Workshop (BARC), 2007, pp. 43-48.
- S. Wang and L. Wang, "Exploiting soft redundancy for error-resilient on-chip memory design," Proc. International Conference on Computer-Aided Design (ICCAD), 2006, pp. 535-540.
- S. Wang and L. Wang, "Joint performance improvement and error tolerance for memory design based on soft indexing," Proc. International Conference on Computer Design (ICCD), 2006, pp. 25-30.
- S. Wang and L. Wang, "Thread-associative memory for multicore and multithreaded computing," Proc. International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 139-142.
- L. Wang, "Human iris identification via low-complexity circular periodicity transform," Proc. of International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2006, pp. 976-979.
- L. Wang and S. Wang, "Adaptive timing for analysis of skew tolerance," Proc. of International Symposium on Circuits and Systems (ISCAS), 2006, pp. 771-774.
- L. Wang and N. Patel, "Reducing error accumulation effect in multithreaded memory systems," Proc. of International Symposium on Circuits and Systems (ISCAS), 2006, pp. 1275-1278.
- L. Wang, "Error-tolerance memory microarchitecture via dynamic multithreading redundancy," Proc. International Conference on Computer Design (ICCD), 2005, pp. 179-184.
- L. Wang, "Algorithm optimization and architectural design of periodicity transform for biometric applications," Proc. of IEEE Workshop on Signal Processing Systems (SiPS), 2005, pp. 585-590.
- L. Wang, "An energy-efficient skew compensation technique for high-speed skew-sensitive signaling," Proc. of International Symposium on Circuits and Systems (ISCAS), 2005, pp. 1658-1661.
- E. Fetzer, L. Wang, and J. Jones, "The multi-threaded, parity-protected 128-word register files on a dual-core Itanium®-family processor," Proc. of International Solid-State Circuits Conference (ISSCC), 2005, pp. 382-383.
- L. Wang and N. R. Shanbhag, "Low-power AEC-based MIMO signal processing for Gigabit Ethernet 1000Base-T transceivers," Proc. International Symposium on Low-Power Electronics and Design (ISLPED), 2001, pp. 334-339.
- L. Wang and N. R. Shanbhag, "Adaptive error cancellation for low-power digital filtering," Proc. of Asilomar Conference on Signals, Systems and Computers, 2000, pp. 1701-1705.
- L. Wang and N. R. Shanbhag, "Low-power signal processing via error-cancellation," Proc. of IEEE Workshop on Signal Processing Systems (SiPS), 2000, pp. 553-562.
- N. R. Shanbhag and L. Wang, "Energy-efficiency bounds for noise-tolerant dynamic circuits," Proc. of International Symposium on Circuits and Systems (ISCAS), 2000, pp. 273-276.
- L. Wang, R. Krishnamurthy, K. Soumyanath, and N. R. Shanbhag, "An energy-efficient leakage-tolerant dynamic circuit technique," Proc. of the 13th Annual IEEE International ASIC/SOC Conference, 2000, pp. 221-225.
- L. Wang and N. R. Shanbhag, "Noise-tolerant dynamic circuit design," Proc. of International Symposium on Circuits and Systems (ISCAS), 1999, pp. 549-552.