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Lei Wang
Assistant Professor
Electrical & Computer Engineering
University of Connecticut
371 Fairfield
Road U-2157
Storrs, CT
06269-2157, USA
Tel:
860-486-3066
Fax:
860-486-2447
E-Mail: leiwang@engr.uconn.edu
Office: ITE 455 |
Lei Wang received the B.S. degree and the M.S. degree from Tsinghua University,
China, in 1992 and 1996, respectively, and the Ph.D. degree from the University of Illinois at Urbana-Champaign
in 2001.
During the summer of 1999, he worked at Microprocessor Research Laboratories,
Intel Corporation, in Hillsboro, OR, where his work involved development of high-speed and noise-tolerant
VLSI circuits and design methodologies. From December 2001 to July 2004, he was with Microprocessor
Technology Laboratories, Hewlett-Packard Company, in Fort Collins, CO, where he participated in the design
of the first dual-core multi-threaded Itanium® Architecture Processor, a joint project between Intel and Hewlett-Packard.
Since August 2004, he is an Assistant Professor with the Department of Electrical and Computer Engineering at
the University of Connecticut.
Education
- PhD,
University of Illinois at Urbana-Champaign, 2001
- MS,
Tsinghua University, Beijing, China, 1996
- BS,
Tsinghua University, Beijing, China, 1992
Appointments
- Performance limits and optimization for molecular computing (supported by NSF)
- Design methodologies for nanoscale ASIC/SOC (supported by TSMC)
- Low-power, high-performance and variation-tolerant microarchitecture (supported by UConn Foundation)
- Signal processing algorithms and architectures for pervasive computing (supported by UConn Foundation)
Selected Publications (Full List)
- S. Wang and L. Wang, "Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency,"
IEEE Trans. on VLSI Systems, accepted as a regular paper.
- L. Wang and N. Patel, "Improving error tolerance for multithreaded register files,"
IEEE Trans. on VLSI Systems, vol. 16, pp. 1009-1020, August 2008.
- S. Wang and L. Wang, "Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation,"
ACM Journal on Emerging Technologies in Computing Systems, accepted as a regular paper.
- Invited paper presentation: S. Wang and L. Wang, "A defect-tolerant memory nanoarchitecture exploiting
hybrid redundancy," IEEE International Conference on Nanotechnology, 2008, to appear.
- W. Tang and L. Wang, "A DSP nanosystem with defect tolerance,"
Proc. IEEE/ACM Symposium on Nanoscale Architectures, 2008, pp. 32-37.
- S. Wang, L. Wang, and F. Jain, "Dynamic redundancy allocation for reliable and high-performance
nanocomputing," Proc. IEEE/ACM Symposium on Nanoscale Architectures, 2007, pp. 1-6.
- J. Dai, L. Wang, and F. Jain, "Analysis of defect tolerance in molecular electronics using information-theoretic measures,"
Proc. IEEE/ACM Symposium on Nanoscale Architectures, 2007, pp. 21-26.
- S. Wang and L. Wang, "Exploiting soft redundancy for error-resilient on-chip memory design,"
Proc. International Conference on Computer-Aided Design (ICCAD), 2006, pp. 535-540.
-
E. Fetzer, L. Wang, and J. Jones, "The multi-threaded, parity protected, 128 word register
files on a dual-core Itanium® Family Processor,"
Proc. IEEE International Solid-State Circuits Conference (ISSCC), 2005, pp. 382-383.
-
L. Wang and N. R. Shanbhag, "Low-power MIMO signal processing,"
IEEE Trans. on VLSI Systems, vol. 11, pp. 434-445, June 2003.
-
L. Wang and N. R. Shanbhag, "Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise,"
IEEE Trans. on VLSI Systems, vol. 11, pp. 254-269, April 2003.
-
L. Wang and N. R. Shanbhag, "Low-power filtering via adaptive error-cancellation,"
IEEE Trans. on Signal Processing, vol. 51, pp. 575-583, February 2003.
-
L. Wang and E. Fetzer, "Receiver and method for mitigating temporary logic transitions," US Patent 7200821, 2007.
-
L. Wang, "Circuit and method for improving noise tolerance in multi-threaded memory circuits," US patent 6850093, 2005.
Teaching
- ECE290/291, Electrical and Computer Engineering Design, Fall 2004
- ECE210W, Electrical Circuits, Spring 2005, Fall 2005
- ECE249, VLSI Design and Simulation, Spring 2006, Spring 2007, Spring 2008
- ECE/CSE257, Numerical Methods in Scientific Computation, Fall 2006
- ECE/CSE280, Digital Design Laboratory, Fall 2007
Professional Services
- TPC Member, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'08)
- TPC Member, IEEE International SOC Conference (SOCC'07, SOCC'08)
- TPC Member, IEEE International Symposium on Quality Electronic Design (ISQED'06, ISQED'07, ISQED'08)
- TPC Member, ACM Great Lakes Symposium on VLSI (GLSVLSI'06, GLSVLSI'07, GLSVLSI'08)
Students
- Shuo Wang, PhD
- Jianwei Dai, PhD
- Weiguo Tang, PhD
- Steven Baird, MS
Alumni
- Niral Patel, MS'07, Bioinformatics Developer, HistoRx, Inc