A Stack Processor
HP3000
This information is in section 11.8.
We discussed previously the ability of a stack to take the place of the
general-purpose register set on a CPU. A stack processor is an elegant form
of processor, as it is the simplest style of processor still capable of
performing general computation.
Some years ago, Hewlett Packard developed the HP3000 CPU, which had an
instruction set designed to process values found on a stack, instead of in
registers.
General architecture
16 bit wide registers, instructions memory is separate from data memory.
Several registers are included for administrative purposes: program base (PB),
program counter (PC), program limit (PL), data base (DB) indicates the start
of the stack (data goes off in other direction), stack limit (SL) indicates
maximum range of stack, stack pointer (SP) [stack grows upward], stack marker
(Q) used to point to the current stack frame.
Programs are relocatable by using the PB register, and always storing address
differences, not absolute addresses, on the stack for return addresses.
Stack instructions
Memory address instructions
The format of memoy addresses is this:
- bits 15-12: opcode
- bit 11: index bit
- bit 10: indirect bit
- bits 9-0: mode and displacement
The mode and displacement field (bits 9 to 0) looks like this:
- PC + relative
- 00ddddddd = [PC] + d
- PC - relative
- 01ddddddd = [PC] - d
- DB + relative
- 10ddddddd = [DB] + d
- Q + relative
- 110dddddd = [Q] + d (error in book, it said [Q] - d)
- Q - relative
- 1110ddddd = [Q] - d
- SP - relative
- 1111ddddd = [SP] - d
QUESTION: why is there no SP + relative format?
There are 11 memory address instructions which use this mode and
displacement field. 5 of these instructions are:
- LOAD: push a memory word onto the stack
- STOR: pop TOS into memory
- ADDM: add memory word to TOS, replace TOS with result
- MPYM: multiply memory word to TOS, replace TOS with LSW of result
- INCM: increment specified memory word
Move instructions
The previous instructions accessed a memory word and the stack. These
instructions access only memory, and addresses are calculated relative to
either the PB or DB registers.
- MOVE: transfer K words from one memory location to another; TOS = K, TOS-1
= first source address (relative to PB or DB), TOS-2 = first destination
address (relative to DB)
Stack instructions
The format of a stack instruction is like this:
- bits 15-12: opcode, = 0000
- bits 11-6: stack opcode A
- bits 5-0: stack opcode B
The two stack opcode fields specify up to two operations to perform on the
stack. This can be done because the instructions need not encode for any
registers, addressing, or data.
Some operations which can be specified in each opcode field:
- ADD: remove and add top 2 stack values, place result on stack
- CMP: remove and compare 2 values, set CC register
- DIV: divide TOS-1/TOS, push quotient, then remainder
- DEL: remove top word from stack
Other operations manipulate more words on the stack.
Benefit: one instruction fetch gets two operations, code density is higher
(fewer words per program).
Packing two stack operations into one instruction is only done if stack
operations must be done. Otherwise, the second opcode field is left empty.
Hardware registers in the stack
If a stack in a CPU is implemented in memory, then there would be a very high
number of memory reads and writes because the stack is taking the place of the
GP registers. An improvement can be realized if the top few stack elements
are placed in hardware registers. Most instructions access only the top few
registers. In the HP3000, the top 4 stack locations are held in 4 hardware
registers.
Since a few of the stack values are held in registers, the SP register is
actually implemented with two registers. One (SM) points to the highest
memory location occupied by the stack, and a 3-bit register (SR) indicates how
many values are in the hardware registers.
Thus, [SP] = [SM] + [SR]