CSE243 Spring 2002
Take-home Make-up Midterm Examination

Jeffrey A. Meunier
Computer Science and Engineering
University of Connecticut
jeffm@cse.uconn.edu

You may use any resource at your disposal to solve these problems, including collaboration with other students, so long as you do no copy answers from one another. All I ask is that you do your own work.

This assignment is due in class Tuesday, April 2, 2002.

Number formats Convert the base-10 numbers in the following table into the correct signed 4-bit binary formats.

base-10 sign & magnitude 1's complement 2's complement

5

-0

-6

IEEE floating point numbers The bit format for IEEE floating point numbers is this:

Sign Exponent Mantissa

1 bit 8 bits 23 bits

z Given the above format, calculate the value of the following 32-bit binary number:
11110000111100000000000000000000
You may leave the number in mantissa/base/exponent notation (m x 10^e), but write both the mantissa and the exponent in base 10.

Assembly language and addressing modes Use the following two tables to compute the final values of registers and memory for the assembly language program shown after the tables.

Memory address Content

0 0

1 1

2 2

3 4

4 8

5 16

6 32

7 64

Register name Value

R0 0

R1 0

R2 0

R3 0

Here is the assembly language program:
```
      Mov #1, R0
      Mov #1, R1
LOOP: Sub (R1), R0
      Add #1, R1
      Cmp R0, #20
      Ble LOOP
      Nop
      Mov R0, (R2)
```
There are tables at the end of this document which may help you.

Instruction decoding Assume a machine word is formatted with the highest-order bits to the left, and the lowest-order bits to the right. Assume the format of a machine instruction is as follows:

The highest 8 bits are the opcode field.
Following the opcode field are zero, one, two, or three operand fields. Each operand field has the following format:
1. The highest two bits are the addressing mode.
2. The next 6 bits are the operand value. If the operand is immediate, treat the value as a signed two's complement number.
Any remaining bits are zero.

Using the tables on page 4, decode the following 32-bit binary words into assembly instructions:

Word	Instruction
00011000010000000101000000000000
11000011001111110000000000000000
00010011100001100100011100000000

Microcode: instruction fetch Give the sequence of microcode operations needed for the complete fetch phase of the execution of a machine instruction (recall everything that needs to happen in the fetch phase). Use the diagram of a single-bus CPU provided in the book on page (?).
Microcode: machine instructions Using the same single-bus CPU diagram, give the sequence of microcode operations for the following three assembly instructions. Use the term ``<fetch>'' to indicatte where an instruction fetch is to take place.
```
START: Mov R0, R1
       Sub (R1), R0
END:   Br R5         ;; Br = unconditional branch
```

Tables

Instruction	Meaning
Add source1, dest	dest = source1 + dest
Ble label	Branch to label if result <= zero
Clr source	Set source to 0
Cmp source1, source2	Compare source1 to source2
Mov source, dest	Copy source to dest
Sub source1, dest	dest = source1 - dest

Addressing
mode	Meaning
syntax
#n	Immediate
Rn	Register
(...)	Indirect

Opcode	Instruction
00000000	Nop
00010001	Add
00010010	Sub
00010011	Mul
00010100	Div
00011000	Cmp
10001000	Mov
11000010	Beq
11000011	Bne

Addressing mode	Binary code
Immediate	00
Register	01
Register Indirect	10
Autoincrement	11

About this document ...

CSE243 Spring 2002
Midterm Examination

This document was generated using the LaTeX2HTML translator Version 2K.1beta (1.47)

The command line arguments were:
latex2html -split 4 -split 1 midterm2.tex

The translation was initiated by Jeffrey A. Meunier on 2002-03-28

Jeffrey A. Meunier 2002-03-28

base-10	sign & magnitude	1's complement	2's complement
5
-0
-6

Sign	Exponent	Mantissa
1 bit	8 bits	23 bits

CSE243 Spring 2002 Take-home Make-up Midterm Examination

About this document ...

CSE243 Spring 2002
Take-home Make-up Midterm Examination