Helena Silva

Assistant Professor

Electrical and Computer Engineering

University of Connecticut 		371 Fairfield Road, Unit 2157
Storrs, CT 06269 USA

Phone: 860-486-5517
Fax: 860-486-2447

helena.silva (at) uconn.edu


Education

Ph.D. Applied Physics, Cornell University (2005)    

 M.S. Applied Physics, Cornell University (2002)

 Licenciatura, Engineering Physics, Universidade Tecnica de Lisboa (1998)

Research Interests

Novel structures and materials for nanoelectronic devices, non-volatile memory devices, electronic transport in the presence of defects and traps, large area electronics, solar cells, sensors, nanofabrication techniques.

Positions Available

There is one position available for a graduate student. Please contact me if you are interested in doing research in these areas.
Publications

13.  Random telegraph signal in nano-scale back-side charge trapping memories.pdf
       H. Silva and S. Tiwari, Appl. Phys. Lett., 88, 10 (2006).

12.  Back-side storage non-volatile memories: ultra-thin silicon single crystal silicon layers with complex thin film structure underneath. pdf
       H. Silva and S. Tiwari, Mater. Res. Soc. Symp. Proc. Vol. 830 D1.4.1 (2005).

11.  Nonvolatile silicon memory at the nanoscale. pdf
       H. Silva, M. K. Kim, U. Avci, A. Kumar and S. Tiwari, MRS Bulletin, November 2004 (2004).

10.  A nano-scale memory and transistor based on back-side trapping. pdf
       H. Silva and S. Tiwari, IEEE Transactions on Nanotechnology, v 3, 2, p. 264 - 269 (2004).

9.    Ultra-short SONOS memories. pdf
       M. K. Kim, S. D. Chae, H. S. Chae, J. H. Kim, Y. S. Jeong, H. Silva, S. Tiwari, IEEE Transactions on Nanotechnology, v 3, 4, 417- 424 (2004).

8.    Few electron memories: finding the compromise between performance, variability and manufacturability at the nano-scale.
       H. Silva, M. K. Kim, A. Kumar, U. Avci and S. Tiwari, IEDM 2003 Technical Digest p. 271-274 (2003).

7.    Scaled front-side and back-side SONOS memories. pdf
       H. Silva, M. K. Kim and S. Tiwari, IEEE International SOI Conference Proceedings (2003).

6.    Write, erase and storage times in nano-crystals memories and the role of interface states. pdf
       J. Wahl, H. Silva, A. Gokirmak, A. Kumar, J. J. Welser and S. Tiwari, IEDM 1999 Technical Digest p. 375-378 (1999).

5.    Ion implantation of microcrystalline silicon for low process temperature top-gate thin film transistors. pdf
       V. Chu, H. Silva, L. M. Redondo, C. Jesus, M. F. Silva, J. C. Soares, J. P. Conde, Thin Solid Films, 337, 1, p. 203-207 (1999).

4.     The effect of hydrogen dilution in hot-wire thin film transistors.
        J. P. Conde, H. Silva, V. Chu, Amorphous and Microcrystalline Silicon Technology 1998 Symposium Proceedings (1999).

3.    Hot-wire amorphous thin film transtors: a comparison between top-gate and bottom-gate structures.
       V. Chu, J. Jarego, T. Silva, J. Bernardo, H. Silva, P. Brogueira, J. P. Conde, MRS Spring 1998 Proceedings (1998).

2.    Amorphous silicon thin film transistors with a hot-wire active layer deposited at a high growth rate.
       V. Chu, J. Jarego, H. Silva, M. Boucinha, P. Brogueira, J. P. Conde, Amorphous and Microcrystalline Silicon Technology 1997 Symposium (1997).

1.    Improved mobility of amorphous silicon thin film transistors deposited by hot-wire chemical vapor deposition on glass substrates. pdf
       V. Chu, J. Jarego, H. Silva, T. Silva, M. Reissner, P. Brogueira and J. P. Conde, Appl. Phys. Lett. 70, p. 2714-2716 (1997).

Teaching

Spring 2007: ECE 100 A Survey of Modern Electronic Technology

Fall 2007    : ECE 205 Electromagnetic Fields and Waves

Memberships

American Physical Society (APS)
Institute of Electrical and Electronics Engineers (IEEE)
Materials Research Society (MRS)