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Journal Papers

[9] RAID0.5: Design and Implementation of a Low Cost Disk Array Data Protection Architecture
John A. Chandy
in Journal of Supercomputing.
Text available at SpringerLink Copyright © 2007 Springer
[8] FPGA Based String Matching for Network Processing Applications
Janardhan Singaraju and John A. Chandy
in Microprocessors and Microsystems, Vol. 32, No. 4, pages 210-222, June 2008.
Text available at ScienceDirect Copyright © 2007 Elsevier Ltd.
[7] Dual Actuator Logging Disk Architecture and Modeling
John A. Chandy
in Journal of Systems Architecture, Vol. 53, No. 12, pages 913-926, December 2007.
Text available at ScienceDirect Copyright © 2007 Elsevier Ltd.
[6] Reliability Tradeoffs in Personal Storage Systems
John A. Chandy and Sumit Narayan
in ACM Operating Systems Review, Vol. 41, No. 1, pages 37-41, January 2007.
PDF (85K)
[5] A CAM-based Keyword Match Processor Architecture
Long Bu and John A. Chandy
in Microelectronics Journal, Vol. 38, No. 8, pages 828-836, August 2006.
Text available at ScienceDirect Copyright © 2005 Elsevier Ltd.
[4] A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee.
in Journal of Parallel and Distributed Computing, Vol. 57, No. 1, pages 65-90, April 1999.
Text available at ScienceDirect Copyright © 1999 Academic Press
[3] An Evaluation of Parallel Simulated Annealing Strategies with Application to Standard Cell Placement
John A. Chandy, Sungho Kim, Balkrishna Ramkumar, Steven Parkes, and Prithviraj Banerjee.
in IEEE Transactions on Computer-Aided Design, April 1997.
PDF (397K)
[2] The PARADIGM Compiler for Distributed-Memory Multicomputers
Prithviraj Banerjee, John A. Chandy, Manish Gupta, Eugene W. Hodges IV, John G. Holm, Antonio Lain, Daniel J. Palermo, Shankar Ramaswamy, and Ernesto Su.
in IEEE Computer, Vol. 28, No. 10, pages 37-47, October 1995.
PDF (1519K), PS (724K)
[1] Design and Evaluation of Gracefully Degradable Disk Arrays
A. L. N. Reddy, John Chandy, and Prithviraj Banerjee.
in Journal of Parallel and Distributed Computing, Vol. 17, No. 1, pp. 28-40, January 1993.
Text available at ScienceDirect © Academic Press

Conference Papers

[28] A Generalized Replica Placement Strategy to Optimize Latency in a Wide Area Distributed Storage System
John A. Chandy
in Proceedings of International Workshop on Data Aware Distributed Computing, Boston, MA, June 2008
PDF (199K)
[27] Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
John A. Chandy and Faquir C. Jain
in Proceedings of International Symposium on Multiple Valued Logic , Dallas, TX, pp. 186-190, May 2008
PDF (322K)
[26] Parity Redundancy in a Clustered Storage System
Sumit Narayan and John A. Chandy
in Proceedings of International Workshop on Storage and Network Architecture and Parallel I/Os, San Diego, CA, Sept. 2007
PDF (257K)
[25] RAID0.5: Active Data Replication for Low Cost Disk Array Data Protection
John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, pp. 963-969, June 2006.
PDF (92K)
[24] A Generic Lookup Cache Architecture for Network Processing Applications
Janardhan Singaraju and John A. Chandy
in Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, NV, pp. 247-248, June 2006.
PDF (39K)
[23] Storage Allocation in Unreliable Peer-to-Peer Systems
John A. Chandy
in Proceedings of International Conference on Dependable Systems and Networks, Philadelphia, PA, June 2006, pp. 227-236.
PDF (166K)
[22] A Quorum Based Content Delivery Architecture
Michael P. Kapralos and John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, June 2005.
PDF (58K)
[21] A Signature Match Processor Architecture for Network Intrusion Detection
Janardhan Singaraju, Long Bu and John A. Chandy
in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, April 2005
PDF (97K)
[20] Trace Based Analysis of File System Effects on Disk I/O
Sumit Narayan and John A. Chandy
in Proceedings of International Symposium on Performance Evaluation of Computer and Telecommunication Systems, San Jose, CA, July 2004
PDF (282K)
[19] A Keyword Match Processor Architecture Using Content Addressable Memory
Long Bu and John A. Chandy
in Proceedings of Great Lakes Symposium on VLSI, Boston, MA, April 2004
PDF (136K)
[18] FPGA Based Network Intrusion Detection using Content Addressable Memories
Long Bu and John A. Chandy
in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, April 2004
PDF (37K)
[17] Parity Redundancy Strategies in a Large Scale Distributed Storage System
John A. Chandy
in Proceedings of IEEE Conference on Mass Storage Systems and Technologies, Adelphi, MD, April 2004, pp. 185-192
PDF (60K)
[16] Data Integrity in a Distributed Storage System
Jonathan D. Bright and John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, June 2003.
PDF (58K)
[15] A Dual Actuator Logging Disk Architecture
John A. Chandy
in Proceedings of IASTED International Conference on Computer Science and Technology, Cancun, Mexico, May 2003.
PDF (63K)
[14] A Scalable Architecture for Clustered Network Attached Storage
Jonathan D. Bright and John A. Chandy
in Proceedings of IEEE/NASA Goddard Conference on Mass Storage Systems and Technologies, San Diego, CA, April 2003, pp. 196-206
PDF (115K)
[13] WADE: A Web-based Automated Parallel CAD Environment
D. R. Chakrabarti, Pramod G. Joisha, John A. Chandy, Dilip Krishnaswamy, Venkat Krishnaswamy, and Prithviraj Banerjee
in Proceedings of HiPC'98 5th International Conference on High Performance Computing, Chennai, India, December 1998
[12] A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee
in Proceedings of International Conference on Computer Design, Austin, TX, October 1997
PDF (192K)
[11] Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors
J. G. Holm, John A. Chandy, Steven Parkes, Sumit Roy, Venkat Krishnaswamy, Gagan Hasteer, and Prithviraj Banerjee
in Proceedings of ACM International Conference on Supercomputing, Vienna, Austria, July 1997
ACM Citation
[10] Parallel Global Routing Algorithms for Standard Cells
Zhaoyun Xing, John A. Chandy, and Prithviraj Banerjee
in Proceedings of International Parallel Processing Symposium, Geneva, Switzerland, April 1997
PDF (87K)
[9] Distributed Object Oriented Data Structures and Algorithms for VLSI CAD
John A. Chandy, Steven Parkes, and Prithviraj Banerjee
in Proceedings of International Workshop on Parallel Algorithms for Irregularly Structured Problems, Santa Barbara, CA, August 1996
PDF (165K)
Slides - PDF (152K)
[8] Parallel Simulated Annealing Strategies for VLSI Cell Placement
John A. Chandy and Prithviraj Banerjee
in Proceedings of the International Conference on VLSI Design, Bangalore, India, January 1996
PDF (176K)
[7] Parallel Algorithms for Logic Synthesis Using the MIS Approach
Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, and Prithviraj Banerjee
in Proceedings of the International Parallel Processing Symposium, Santa Barbara, CA, April 1995
PDF (1103K)
[6] The PARADIGM Compiler for Distributed-Memory Message Passing Multicomputers
P. Banerjee, J. A. Chandy, M. Gupta, J. G. Holm, A. Lain, D. J. Palermo, S. Ramaswamy, and E. Su.
in the Proceedings of the First International Workshop on Parallel Processing, Bangalore, India, December 1994, pp. 322-330.
PS (271K)
[5] A Library-based Approach to Portable, Parallel, Object-Oriented Programming: Interface, Implementation, and Application
Steven Parkes, John A. Chandy, and Prithviraj Banerjee
in Proceedings of Supercomputing '94, Washington, DC, November 1994, pp. 69-78.
PDF (1028K), Slides - PS (208K)
[4] Communication Optimizations for Distributed Memory Multicomputers used in the PARADIGM Compiler
D. J. Palermo, E. Su, J. A. Chandy, and P. Banerjee.
in Proceedings of the International Conference on Parallel Processing, St. Charles, IL, August 1994, pp. II:1-10.
PS (555K)
[3] ProperPLACE: A Portable Parallel Algorithm for Cell Placement
Sungho Kim, John A. Chandy, Steven Parkes, Balkrishna Ramkumar, and Prithviraj Banerjee
in Proceedings of the International Parallel Processing Symposium, Cancun, Mexico, April 1994.
PDF (229K)
[2] Reliability Evaluation of Disk Array Architectures
John A. Chandy and Prithviraj Banerjee.
in Proceedings of the International Conference on Parallel Processing, St. Charles, IL, August 1993, pp. I:263-267.
PDF (160K)
[1] Failure Evaluation of Disk Array Organizations
John Chandy and A. L. N. Reddy
in Proceedings of the International Conference on Distributed Computing Systems, Pittsburgh, PA, May 1993.
PDF (174K)

Technical Reports

A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee
Technical Report CPDC-TR-9801-001, January 1998, Center for Parallel and Distributed Computing, Northwestern University, Evanston, IL
PS (147K)

Parallel Algorithms for Standard Cell Placement Using Simulated Annealing
John A. Chandy
PhD dissertation, Department of Electrical Engineering, University of Illinois, July 1996, Technical Report CRHC-96-10/UILU-ENG-96-2216
PDF (758K)

ProperCAD II: A Run-Time Library for Portable, Parallel, Object-Oriented Programming with Applications to VLSI CAD
Steven Parkes, John A. Chandy, and Prithviraj Banerjee
Technical Report CRHC-93-22/UILU-ENG-93-2250, December 1993, Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
PDF (481K)

An Evaluation of Disk Array Reliability and Performance
John A. Chandy
M.S. thesis, Department of Electrical Engineering, University of Illinois, Urbana, IL, December 1992, Technical Report CRHC-92-28