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University of Connecticut School of Engineering John A. Chandy

Publications

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2016

DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication
Fatemeh Tehranipoor, Nima Karimian, Wei Yan, and John A. Chandy
in IEEE Transactions on VLSI Systems , To Appear
Text available at IEEE XPlore Copyright © 2016 IEEE

Adding Data Analytics Capabilities to Scaled-out Object Store
Cengiz Karakoyunlu, John A. Chandy, and Alma Riska
in Journal of Systems and Software , vol. 121, pp. 16-27, November 2016.
Text available at ScienceDirect Copyright © 2016 Elsevier Ltd.

A Survey on Chip to System Reverse Engineering
S.E. Quadir, J. Chen, D. Forte, N. Asadizanjani, S. Shahbazmohamadi, L. Wang, John Chandy, and M. Tehranipoor
in ACM Journal on Emerging Technologies in Computing Systems , vol. 13, no. 1, article 6, May 2016
Text available at ACM Digital Library Copyright © 2016 ACM

Robust hardware true random number generators using DRAM remanence effects
Fatemeh Tehranipoor, Wei Yan, and John A. Chandy
in Proceedings of IEEE International Symposium on Hardware Oriented Security and Trust McLean, VA, pp. 79-84, May 2016.
DOI

Exploiting User Metadata for Energy-Aware Node Allocation in a Cloud Storage System
Cengiz Karakoyunlu and John A. Chandy
in Journal of Computer and System Sciences , vol. 82, no. 2, pp. 282-309, March 2016.
Text available at ScienceDirect Copyright © 2016 Elsevier Ltd.


2015

A Novel Way to Authenticate Untrusted Integrated Circuits
Wei Yan, Fatemeh Tehranipoor, and John A. Chandy
in Proceedings of International Conference on Computer-Aided Design Austin, TX, pp. 132-138, November 2015.
DOI

Leveraging Checkpoint/Restore to Optimize Utilization of Cloud Compute Resources
Rohit Mehta and John A. Chandy
in Proceedings of IEEE Workshop on Cloud-Based Networks and Applications Clearwater Beach, FL, pp. 714-721, October 2015.
DOI

Novel Multiplexer Design Using Multi-State Spatial Wavefunction-Switched (SWS) FETs
Pial Mirdha, Murali Lingalugari, Evan K. Heller, John A. Chandy, and Faquir C. Jain
in International Journal of High Speed Electronics and Systems , vol. 24, issue 03, no. 04, Sept./Dec. 2015.
Text available Copyright © 2015 World Scientific Publishing

Si and InGaAs Spatial Wavefunction-Switched (SWS) FETs with II–VI Gate Insulators: An Approach to the Design and Integration of Two-Bit SRAMs and Binary CMOS Logic
Faquir Jain, Pik-Yiu Chan, Murali Lingalugari, Jun Kondo, Ernesto Suarez, Pawan Gogna, John Chandy, and Evan Heller
in Journal of Electronic Materials , vol. 44, no. 9, pp. 3109-3115, September 2015.
Text available at SpringerLink Copyright © 2015 Springer

Hardware Hacking: An Approach to Trustable Computing Systems Security Education
John A. Chandy, Zhijie Shi, Mohammad Tehranipoor, Megan Welsh, Chujiao Ma, Qihang Shi, and Ujjwal Guin
in Colloquium for Information Systems Security Education Las Vegas, NV, June 2015.

DRAM based Intrinsic Physical Unclonable Functions for System Level Security
Fatemeh Tehranipoor, Nima Karimian, Kan Xiao, and John A. Chandy
in Proceedings of ACM Great Lakes Symposium on VLSI Pittsburgh, PA,pp. 15-20, May 2015.
DOI

Active Storage Networks: Using Embedded Computation in the Network Switch for Cluster Data Processing
Janardhan Singaraju, Ajithkumar Thamarakuzhi and John A. Chandy
in Future Generation Computer Systems , vol. 45, pp. 149-160, April 2015.
Text available at ScienceDirect Copyright © 2015 Elsevier Ltd.

Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs
Supriya Karmakar, John A. Chandy, and Faquir C. Jain
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 23, no. 4, pp. 609-618, April 2015.
Text available at IEEE XPlore Copyright © 2015 IEEE


2014

Using an Object-Based Active Storage Framework to Improve Parallel Storage
Cengiz Karakoyunlu, Michael Runde, and John A. Chandy
in Proceedings of Workshop on Interfaces and Architectures for Scientific Data Storage Minneapolis, MN, Sept. 2014.
DOI

Creating a programmable object storage stack
Orko Momin, Cengiz Karakoyunlu, Michael T. Runde, and John A. Chandy
in Proceedings of the Programmable File Systems Workshop , Vancouver, CANADA, June 2014.
DOI


2013

Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic
Pawan Gogna, Ernesto Suarez, Murali Lingalugari, John Chandy, Evan Heller, E.-S. Hasaneen, and Faquir C. Jain
in Journal of Electronic Materials , vol. 42, no. 11, pp. 3337-3343, November 2013.
Text available at SpringerLink Copyright © 2013 Springer

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers,” in
Faquir Jain, Pik-Yiu Chan, Ernesto Suarez, Murali Lingalugari, Jun Kondo, Pawan Gogna, Barry Miller, John Chandy, and Evan Heller
in Journal of Electronic Materials , vol. 42, no. 11, pp. 3191-3202, November 2013.
Text available at SpringerLink Copyright © 2013 Springer.

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators
Murali Lingalugari, Kavitha Baskar, Pik-Yiu Chan, P. Dufilie, Ernesto Suarez, John Chandy, Evan Heller, E.-S. Hasaneen, and Faquir C. Jain
in Journal of Electronic Materials , vol. 42, no. 11, pp. 3156-3163, November 2013
Text available at SpringerLink Copyright © 2013 Springer

An object interface storage node for clustered file systems
Orko Momin and John A. Chandy
in Proceedings of IEEE Cluster Computing , Indianapolis, IN, September 2013.
DOI

Optimizations on a Parallel File System Integrated with Object-Based Storage Devices
Cengiz Karakoyunlu and John A. Chandy
in Proceedings of IEEE Cluster Computing , Indianapolis, IN, September 2013.
DOI

Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs
Supriya Karmakar, John A. Chandy, and Faquir C. Jain
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 21, no. 5, pp. 793-806, May 2013
Text available at IEEE XPlore Copyright © 2013 IEEE


2012

A Case for Optimistic Coordination in HPC Storage Systems
Philip Carns, Kevin Harms, Dries Kimpe, Robert Ross, Justin Wozniak, Lee Ward, Matthew Curry, Ruth Klundt, Geoff Danielson, Cengiz Karakoyunlu, John Chandy, Bradley Settlemeyer, and William Gropp
in Proceedings of Petascale Data Storage Workshop , Salt Lake City, UT, November 2012.
DOI

Quaternary Logic and Applications using Multiple Quantum Well Based SWSFETs
Pawan Gogna, Murali Lingalugari, John A. Chandy, Evan Heller, E.-S. Hasaneen, and Faquir Jain
in International Journal of VLSI Design and Communication Systems , vol. 3, no. 5, pp. 27-42, October 2012.
PDF Copyright © 2012 AIRCC Publishing

Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II-VI Barrier Layers
Faquir Jain, Supriya Karmakar, Pik-Yiu Chan, Ernesto Suarez, Mukesh Gogna, John A. Chandy, and Evan Heller
in Journal of Electronic Materials , vol. 41, no. 10 pp. 2775-2784, October 2012.
Text available at SpringerLink Copyright © 2012 Springer

Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors
Supriya Karmakar, John A. Chandy, Mukesh Gogna, and Faquir C. Jain
in Journal of Electronic Materials , vol. 41, no. 8 pp. 2184-2192, Aug. 2012
Text available at SpringerLink Copyright © 2012 Springer

Techniques for an Energy Aware Parallel File System
Cengiz Karakoyunlu and John A. Chandy
in Proceedings of International Green Computing Conference: Energy Consumption and Reliability of Storage Systems , San Jose, CA, pp. 13-17, June 2012.
DOI

An Active Storage Framework for Object Storage Devices
Michael T. Runde, Wesley G. Stevens, Paul A. Wortman, and John A. Chandy
in Proceedings of IEEE Conference on Massive Data Storage, Pacific Grove, CA, April 2012
PDF (351K)

A Non-blocking Switching Network and Routing Algorithm for On-Chip Networks
Ajithkumar Thamarakuzhi and John A. Chandy
in Procedia Engineering , vol. 30, pp. 997-1004, 2012.
Text available at ScienceDirect Copyright © 2012 Elsevier Ltd.


2011

2-Dilated Flattened Butterfly: A Nonblocking Switching Topology for High-Radix Networks
Ajithkumar Thamarakuzhi and John A. Chandy
in Computer Communications , vol. 34, no. 15, pp. 1822-1835, September 15, 2011.
Text available at ScienceDirect Copyright © 2011 Elsevier Ltd.

A Non-blocking Switching Network and Routing Algorithm for On-Chip Networks
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the International Conference on Communication Technology and System Design , December 2011
PDF

Spatial Wavefunction-Switched (SWS)-FET: A Novel Device to Process Multiple Bits Simultaneously with Sub-Picosecond Delays
S. Karmakar, J. A. Chandy, and F.C. Jain
in International Journal of High Speed Electronics and Systems , vol. 20, no. 3, pp. 653-668, September 2011.
Text available at Link Copyright © 2011 World Scientific Publishing

Application of 25 nm Quantum Dot Gate FETs to the Design of ADC and DAC Circuits
F.C. Jain, J. A. Chandy, B. Miller, E.-S. Hasaneen, and E. Heller
in International Journal of High Speed Electronics and Systems , vol. 20, no. 3, pp. 641-652, September 2011.
Text available at Link Copyright © 2011 World Scientific Publishing

Spatial Wavefunction Switched (SWS) InGaAs FETs with II-VI Gate Insulators
F.C. Jain, B. Miller, E. Suarez, P-Y. Chan, S. Karmakar, F. Al-Amoody, M. Gogna, J. Chandy, and E. Heller
in Journal of Electronic Materials , vol. 40, no. 8, pp. 1717-1726, Aug. 2011
Text available at SpringerLink Copyright © 2011 Springer

Active Storage Networks for Accelerating K-Means Data Clustering
Janardhan Singaraju and John A. Chandy
in Proceedings of the Symposium on Applied Reconfigurable Computing , March 2011
PDF

Adaptive Load Balanced Routing for 2-Dilated Flattened Butterfly Switching Network
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the International Conference on Networks, January 2011, Best Paper Award
PDF


2010

Parallel data sort using networked FPGAs
Janardhan Singaraju and John A. Chandy
in Proceedings of the International Conference on ReConFigurable Computing and FPGAs , December 2010
PDF

Design and Implementation of a Nonblocking 2-Dilated Flattened Butterfly Switching Network
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the IEEE Latin American Conference on Communications, September 2010
PDF

Scaling the NetFPGA switch using Aurora over SATA
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the NetFPGA Developers Workshop, August 2010
PDF

User space storage system stack modules with file level control
Sumit Narayan, Rohit K. Mehta, and John A. Chandy
in Proceedings of the Annual Linux Symposium, July 2010
PDF

I/O Characterization on a Parallel File System
Sumit Narayan and John A. Chandy
in Proceedings of the International Symposium on Performance Evaluation of Computer and Telecommunication Systems, July 2010
PDF

3-state Quantum Dot Gate FETs in Desigining High Sampling Rate ADCs
S. Karmakar, John A. Chandy, and F.C. Jain
in Proceedings of the NST Nanotechnology Conference and Expo, June 2010

2-Dilated Flattened Butterfly: A Nonblocking Switching Network
Ajithkumar Thamarakuzhi and John A. Chandy
in Proceedings of the International Conference on High Performance Switching and Routing, June 2010
PDF


2009

Uncovering Errors: The Cost of Detecting Silent Data Corruption
Sumit Narayan, John A. Chandy, Sam Lang, Philip Carns, and Rob Ross
in Proceedings of the 4th Petascale Data Storage Workshop (PDSW) held in conjunction with IEEE/ACM Supercomputing 2009, Portland, OR. November 2009
PDF

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators
F.C. Jain, E. Suarez, M. Gogna, F. Alamoody, D. Butkiewicus, R. Hohner, T. Liaskas, S. Karmakar, P.-Y. Chan, B. Miller, J. Chandy, and E. Heller
in Journal of Electronic Materials, vol. 38, no. 8, pp. 1574-1578, August 2009
Text available at SpringerLink Copyright © 2009 Springer

FEARLESS: Flash Enabled Active Replication of Low End Survivable Storage
Vamsi Kundeti and John A. Chandy
in Proceedings of the International Workshop on Integrating Solid-state Memory into the Storage Hierarchy (WISH), Washington, DC, March 2009
PDF

Hardware parallelism vs. software parallelism
John A. Chandy and Janardhan Singaraju
in Proceedings of the USENIX Workshop on Hot Topics in Parallelism (HotPar), Berkeley, CA, March 2009
PDF


2008

Modeling and Fabrication of Cladded Ge Quantum Dot Gate Silicon MOSFETs Exhibiting 3-State Behavior
F. Jain, M. Gogna, F. Alamoody, S. Karmakar, E. Suarez, J. Chandy, and E. Heller
in Proceedings of MRS Fall Meeting Symposium A: Performance and Reliability of Semiconductor Device, December 2008

RAID0.5: Design and Implementation of a Low Cost Disk Array Data Protection Architecture
John A. Chandy
in Journal of Supercomputing, vol. 46, no. 2, pp. 108-123, November 2008
Text available at SpringerLink Copyright © 2007 Springer

Active Storage using Object-Based Devices
Tina Miriam John, Anuradharthi Thiruvenkata Ramani, and John A. Chandy
in Proceedings of International Workshop on High Performance I/O Systems and Data Intensive Computing (HiperIO), Tsukuba, Japan, October 2008
PDF

A Generalized Replica Placement Strategy to Optimize Latency in a Wide Area Distributed Storage System
John A. Chandy
in Proceedings of International Workshop on Data Aware Distributed Computing, Boston, MA, June 2008
PDF (199K)

FPGA Based String Matching for Network Processing Applications
Janardhan Singaraju and John A. Chandy
in Microprocessors and Microsystems, Vol. 32, No. 4, pages 210-222, June 2008.
Text available at ScienceDirect Copyright © 2007 Elsevier Ltd.

Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
John A. Chandy and Faquir C. Jain
in Proceedings of International Symposium on Multiple Valued Logic , Dallas, TX, pp. 186-190, May 2008
PDF (322K)


2007

Dual Actuator Logging Disk Architecture and Modeling
John A. Chandy
in Journal of Systems Architecture, Vol. 53, No. 12, pages 913-926, December 2007.
Text available at ScienceDirect Copyright © 2007 Elsevier Ltd.

Parity Redundancy in a Clustered Storage System
Sumit Narayan and John A. Chandy
in Proceedings of International Workshop on Storage and Network Architecture and Parallel I/Os, San Diego, CA, Sept. 2007
PDF (257K)

Reliability Tradeoffs in Personal Storage Systems
in ACM Operating Systems Review, Vol. 41, No. 1, pages 37-41, January 2007.
PDF (85K)


2006

A CAM-based Keyword Match Processor Architecture
Long Bu and
John A. Chandy
in Microelectronics Journal, Vol. 38, No. 8, pages 828-836, August 2006.
Text available at ScienceDirect Copyright © 2005 Elsevier Ltd.

RAID0.5: Active Data Replication for Low Cost Disk Array Data Protection
John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, pp. 963-969, June 2006.
PDF (92K)

A Generic Lookup Cache Architecture for Network Processing Applications
Janardhan Singaraju and John A. Chandy
in Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, NV, pp. 247-248, June 2006.
PDF (39K)

Storage Allocation in Unreliable Peer-to-Peer Systems
John A. Chandy
in Proceedings of International Conference on Dependable Systems and Networks, Philadelphia, PA, June 2006, pp. 227-236.
PDF (166K)


2005

A Quorum Based Content Delivery Architecture
Michael P. Kapralos and
John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, June 2005.
PDF (58K)

A Signature Match Processor Architecture for Network Intrusion Detection
Janardhan Singaraju, Long Bu and John A. Chandy
in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, April 2005
PDF (97K)


2004

Trace Based Analysis of File System Effects on Disk I/O
Sumit Narayan and John A. Chandy
in Proceedings of International Symposium on Performance Evaluation of Computer and Telecommunication Systems, San Jose, CA, July 2004
PDF (282K)

A Keyword Match Processor Architecture Using Content Addressable Memory
Long Bu and John A. Chandy
in Proceedings of Great Lakes Symposium on VLSI, Boston, MA, April 2004
PDF (136K)

FPGA Based Network Intrusion Detection using Content Addressable Memories
Long Bu and John A. Chandy
in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, April 2004
PDF (37K)

Parity Redundancy Strategies in a Large Scale Distributed Storage System
John A. Chandy
in Proceedings of IEEE Conference on Mass Storage Systems and Technologies, Adelphi, MD, April 2004, pp. 185-192
PDF (60K)


2003

Data Integrity in a Distributed Storage System
Jonathan D. Bright and John A. Chandy
in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, June 2003.
PDF (58K)

A Dual Actuator Logging Disk Architecture
John A. Chandy
in Proceedings of IASTED International Conference on Computer Science and Technology, Cancun, Mexico, May 2003.
PDF (63K)

A Scalable Architecture for Clustered Network Attached Storage
Jonathan D. Bright and John A. Chandy
in Proceedings of IEEE Symposium on Mass Storage Systems and Technologies, San Diego, CA, April 2003, pp. 196-206
PDF (115K)


1999

A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee.
in Journal of Parallel and Distributed Computing, Vol. 57, No. 1, pages 65-90, April 1999.
Text available at ScienceDirect copyright Academic Press


1998

WADE: A Web-based Automated Parallel CAD Environment
D. R. Chakrabarti,
Pramod G. Joisha, John A. Chandy, Dilip Krishnaswamy, Venkat Krishnaswamy, and Prithviraj Banerjee
in Proceedings of HiPC'98 5th International Conference on High Performance Computing, Chennai, India, December 1998

A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee
Technical Report CPDC-TR-9801-001, January 1998, Center for Parallel and Distributed Computing, Northwestern University, Evanston, IL
PS (147K)


1997

A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement
John A. Chandy and Prithviraj Banerjee
in Proceedings of International Conference on Computer Design, Austin, TX, October 1997
PDF (192K)

Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors
J. G. Holm, John A. Chandy, Steven Parkes, Sumit Roy, Venkat Krishnaswamy, Gagan Hasteer, and Prithviraj Banerjee
in Proceedings of ACM International Conference on Supercomputing, Vienna, Austria, July 1997
ACM Citation

An Evaluation of Parallel Simulated Annealing Strategies with Application to Standard Cell Placement
John A. Chandy, Sungho Kim, Balkrishna Ramkumar, Steven Parkes, and Prithviraj Banerjee.
in IEEE Transactions on Computer-Aided Design, April 1997.
PDF (397K)

Parallel Global Routing Algorithms for Standard Cells
Zhaoyun Xing, John A. Chandy, and Prithviraj Banerjee
in Proceedings of International Parallel Processing Symposium, Geneva, Switzerland, April 1997
PDF (87K)


1996

Distributed Object Oriented Data Structures and Algorithms for VLSI CAD
John A. Chandy, Steven Parkes, and Prithviraj Banerjee
in Proceedings of International Workshop on Parallel Algorithms for Irregularly Structured Problems, Santa Barbara, CA, August 1996
PDF (165K)
Slides - PDF (152K)

Parallel Algorithms for Standard Cell Placement Using Simulated Annealing
John A. Chandy
PhD dissertation, Department of Electrical Engineering, University of Illinois, July 1996, Technical Report CRHC-96-10/UILU-ENG-96-2216
PDF (758K)

Parallel Simulated Annealing Strategies for VLSI Cell Placement
John A. Chandy and Prithviraj Banerjee
in Proceedings of the International Conference on VLSI Design, Bangalore, India, January 1996
PDF (176K)


1995

The PARADIGM Compiler for Distributed-Memory Multicomputers
Prithviraj Banerjee, John A. Chandy, Manish Gupta, Eugene W. Hodges IV, John G. Holm, Antonio Lain, Daniel J. Palermo, Shankar Ramaswamy, and Ernesto Su.
in IEEE Computer, Vol. 28, No. 10, pages 37-47, October 1995.
PDF (1519K), PS (724K)

Parallel Algorithms for Logic Synthesis Using the MIS Approach
Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, and Prithviraj Banerjee
in Proceedings of the International Parallel Processing Symposium, Santa Barbara, CA, April 1995
PDF (1103K)


1994

The PARADIGM Compiler for Distributed-Memory Message Passing Multicomputers
P. Banerjee, J. A. Chandy, M. Gupta, J. G. Holm, A. Lain, D. J. Palermo, S. Ramaswamy, and E. Su.
in the First International Workshop on Parallel Processing, pages 322-330, Bangalore, India, December 1994.
PS (271K)

A Library-based Approach to Portable, Parallel, Object-Oriented Programming: Interface, Implementation, and Application
Steven Parkes, John A. Chandy, and Prithviraj Banerjee
in Proceedings of Supercomputing '94, Washington, DC, November 1994, pp. 69-78.
PDF (1028K), Slides - PS (208K)

Communication Optimizations for Distributed Memory Multicomputers used in the PARADIGM Compiler
D. J. Palermo, E. Su, J. A. Chandy, and P. Banerjee.
in Proceedings of the 23rd International Conference on Parallel Processing, pages II:1-10, St. Charles, IL, August 1994.
PS (555K)

ProperPLACE: A Portable Parallel Algorithm for Cell Placement
Sungho Kim, John A. Chandy, Steven Parkes, Balkrishna Ramkumar, and Prithviraj Banerjee
in Proceedings of the International Parallel Processing Symposium, Cancun, Mexico, April 1994.
PDF (229K)


1993

ProperCAD II: A Run-Time Library for Portable, Parallel, Object-Oriented Programming with Applications to VLSI CAD
Steven Parkes, John A. Chandy, and Prithviraj Banerjee
Technical Report CRHC-93-22/UILU-ENG-93-2250, December 1993, Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
PDF (481K)

Reliability Evaluation of Disk Array Architectures
John A. Chandy and Prithviraj Banerjee.
in Proceedings of the 22nd International Conference on Parallel Processing, St. Charles, IL, August 1993.
PDF (160K)

Failure Evaluation of Disk Array Organizations
John Chandy and A. L. N. Reddy
in Proceedings of the International Conference on Distributed Computing Systems, Pittsburgh, PA, May 1993.
PDF (174K)

Design and Evaluation of Gracefully Degradable Disk Arrays
A. L. N. Reddy, John Chandy, and Prithviraj Banerjee.
in Journal of Parallel and Distributed Computing, Vol. 17, No. 1, pp. 28-40, January 1993.
Text available at ScienceDirect © Academic Press


1992

An Evaluation of Disk Array Reliability and Performance
John A. Chandy
M.S. thesis, Department of Electrical Engineering, University of Illinois, Urbana, IL, December 1992, Technical Report CRHC-92-28