ECE311 Computer Engineering Seminar

 

Time and Location: Tue. 4pm-5pm, ITEB119

 

 

Faculty

 

John A. Chandy, Jun-Hong Cui, Yunsi Fei, Jerry Shi, Mohammad Tehranipoor, Lei Wang

 

 

Course Description

 

This ECE Computer Engineering Seminar meets weekly. In each meeting, a presentation addressing the recent work or new research directions in the area of computer engineering will be given by a faculty member or a graduate student. Topics include VLSI design, EDA, embedded systems, computer architecture, networking, and operating systems.

 

Presentation Schedule

 

Check the preliminary schedule. Note that this is subject to change.

 

08/29

John Chandy

Introduction

09/05

Jeremy Lee

Protecting IPs Against Scan-Based Side-Channel Attacks

09/12

Nisar Ahmed

At-speed Transition Fault Testing Using Low-Cost Testers
Abstract: With today's design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launchoff-shift method has several advantages over the launch-offcapture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encapsulated in the test data and transferred during the scan operation. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practiceoriented and suitable for use in an industrial flow.

09/19

Shuo Wang

Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing
Abstract: Memory design is facing the dual challenges of performance improvement and error tolerance due to a combination of technology scaling and higher levels of integration. To address these challenges, we propose a new memory microarchitecture referred to as the soft indexing. The proposed technique allocates memory resources in a self-adaptive manner in accordance with runtime program variations, thereby achieving efficient memory access and effective error protection in a coherent manner.

09/26

Niral Patel

DFM: An Overview
Abstract: Design For Manufacturability (DFM) has emerged as a major driver as the semiconductor industry continues on its historic scaling trend. The International Technology Roadmap for Semiconductors (ITRS) Design Group has engaged in a major overhaul of the Design Technology Roadmap, including a completely new section focused on DFM. DFM in its broadest definition can be seen as the manipulation of data anywhere in the design-to silicon flow with the goal of optimizing chip performance, yield, and cost. The talk will focus on the current trends and challenges faced in the field of DFM.

10/03

Sumit Narayan

Distributed Storage Architectures
Abstract: Network content is expected to grow continuously for the next several years. It hence becomes increasingly important for researchers in storage domain to design comprehensive strategies to optimize network storage infrastructure that will enable scalability, reliability, performance, availability, affordability and manageability. This presentation would talk about some of the new strategies for large-scale data storage (object-based storage) and their intelligence to make them self-configuring, self-healing, self-optimizing and self-protecting.

10/10

Zheng (James) Peng

System Software Techniques for Low-Power Operation in Wireless Sensor Networks (by P.K. Dutta et al)
Abstract: The operation of wireless sensor networks is fundamentally constrained by available energy sources. The underlying hardware determines the power draw of each possible mode of operation. System software attempts maximize the use of the lowest possible modes of each of the subsystems. This tutorial paper describes the system software techniques used at several levels. At the application sensing level, this includes duty-cycling, sensor hierarchy, and aggregation. At the communication level, it includes low-power listening, communication scheduling, piggybacking, post-hoc synchronization, and power-aware routing. At the node OS level, it includes event driven execution with split-phase operation and cooperative power management interfaces. At the lowest level, it includes management of primary and secondary energy storage devices coupled with intelligent charge transfer scheduling. All of these aspects must be integrated in a systematic software framework.

10/17

Hai Lin

Fine-grain Sleep Transistor Insertion for Leakage Power Reduction in Multi-threshold CMOS technology
Abstract: With the growing scaling of technology, leakage power dissipation has become a critical issue of VLSI Circuit & System designs. Multi-threshold CMOS technology leads to about 10X leakage reduction in circuit standby mode. In this presentation, we will talk about reducing leakage current through fine-grain High-VTH sleep transistor (ST) insertion which makes it possible and efficient to guarantee circuit functionality at high speed and improves circuit noise margins while reducing the leakage to a satisfactory level. The leakage current reduction modeling problem will be discussed and a mixed-integer linear programming (MLP) solution in order to simultaneously choose where to add the sleep transistors and the sleep transistors sizes optimally will be introduced.

10/24

Chulwoo Park

Power analysis of wireless sensor networks
Abstract: Power analysis becomes a more and more important topic for the wireless sensor network research due to the constraint of battery capacity. In this presentation, the general characteristics of wireless sensor networks related to power consumption are introduced. Methods on how to measure the power consumption of sensors and networks are also covered. Finally several research approaches with different measuring methods and limitations are presented.

10/31

Xuan Guan

Analysis of the Register File Power Reduction Techniques in ASIP Design
Abstract: Power consumption has become one of the most important design issues for microprocessors design targeted to multimedia and handheld applications. This is particularly interesting for architectural design exploration targeting application-specific integrated processors (ASIPs), which offer a high flexibility and performance at a relatively low cost. Register files represent a substantial portion of the energy budget in modern microprocessors, about 16% of the total processor power and 42% of the data path power. Here we summarized several register file power reduction techniques for ASIP Design, including reduce the physical register space requirement by using a 16-bit ISA synthesis; Reduce the number of accesses to register file by bypass and data forwarding; Relax register file port constraints by exploiting pipelining; Using shadow registers to avoid replication of Register File; Precise read control avoids fetching unused operands; Latch clock gating disables latch clocks when operands are not needed, Bypass R0 treats accesses to R0 separately; Split bitline reduces access energy for frequently-used registers, and read caching avoids register file reads when the same register is read twice in succession. We also explore the idea of Instruction Register file, which by packing instructions into Regfile can achieve power reduction by fewer accesses to the instruction cache and memory. Based on the above analysis, hope it could give us an idea of building a more accurate energy estimation model for ASIP accounting the influence of Register File.

11/07

Hai Yan

Studying software implementations of Elliptic Curve Cryptography
Abstract: Elliptic Curve Cryptography (ECC) is a promising alternative for public-key algorithms in resource constrained systems because it provides a similar level of security with much shorter keys than conventional integer-based public-key algorithms. ECC over binary field is of special interest because the operations in binary field are thought more space and time efficient. However, the software implementations of ECC over binary field are still slow, especially on low-end processors in small computing devices such as sensor nodes. In this paper, we studied software implementations of ECC. We first investigated whether some architectural parameters such as word size may affect the choice of algorithms when implementing ECC with software. We identified a set of algorithms for ECC implementation on low-end processors. We also examined several improvements to the instruction set architecture of an 8-bit processor and studied their impact on the performance of ECC. Although some improvements bring a significant speedup on processors with large word sizes, they are not very effective for 8-bit processors.

11/14

Jennifer Dworak (Brown University)

(in ITE336)

Fortuitous Detection of Untargeted Defects through Weighted Random Patterns Generated with Partial Fault Targeting
Abstract: Historically, test pattern sets have been generated by targeting single stuck-at faults, and the accompanying test set quality has been estimated based upon stuck-at fault coverage. However, many defects exhibit behavior that does not perfectly match any single stuck-at fault, and these defects must be detected fortuitously instead. Site observation is a common requirement for the detection of different types of defects while the conditions that must be satisfied for excitation vary. As a result, multiple site observations accompanied by good excitation balance significantly improve the detection of untargeted defects. Unfortunately, such test sets tend to be significantly longer than a single-detect stuck-at fault test setóleading to problems with test data volume. In this presentation, we will investigate the defect detection ability of weighted random pattern sets generated through partial fault targeting and will show that they may be more effective than a deterministic test set that guarantees the same number of minimal fault detections.

11/28

Zhong Zhou

Energy-Efficient Cooperative Communication based on Power Control and Selective Relay in Wireless Sensor Networks
Abstract: Cooperative communication with single relay selection is a simple and efficient communication scheme for energy-constrained networks. In this paper, we combine the selective relay cooperative communication with physical-layer power control. Based on the MAC layer RTS-CTS signaling, a set of potential relays determine the needed transmission power to participate in the cooperative communication. Within a competition window of fixed length, the ``best'' relay is selected in a distributed fashion with minimum signaling overhead. For relay selection, we study two policies, one is to minimize the energy consumption per data packet while the other is to maximize the network lifetime. Numerical results confirm significant energy savings and network lifetime increase of the proposed scheme relative to direct transmission alternatives.

11/28

Fan Zhang

Key Management Protocols in Sensor Networks
Abstract: For the security of sensor networks symmetric key protocols are used due to the limited resources of the nodes. An important issue is how to distribute the keys to the nodes, such that any pair of nodes can share a secret key. There are three main kinds of symmetric key establishment schemes: Full Pairwise scheme, KDC-based scheme, and Random Key Predistribution scheme. These existing schemes incur a linearly increasing cost ?O(n) in either communications per node or memory per node. Some researchers designed a new scheme (PIKE) which is O(n^1/2) in both communications and memory. In this paper, we propose a new key establishment scheme which could reduce both the communications per node and memory per node to O(log n).