This ECE Computer Engineering Seminar meets weekly. In
each meeting, a presentation addressing the recent work or new research
directions in the area of computer engineering will be given by a faculty
member or a graduate student. Topics include VLSI design, EDA, embedded
systems, computer architecture, networking, and operating systems.
Check the preliminary schedule. Note that this is subject to
change.
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01/24
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Michael Kapralos
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Hardware
Implementations of Transcendental Functions
Abstract: Transcendental functions such as log, sine, cosine, tangent, and
algebraic functions such as square root, and inverse square root are all
crucial in common computations. There are 2 common schools of thought,
CORDIC-type methods which are accurate and compact, but extremely slow;
while table based methods are accurate, but require a great deal of
storage room. As a result, a compromise involving moderately sized
tables and with a reasonable speed while maintaining good accuracy is
very important. In this talk, different methods for log, inverse log,
and inverse will be discussed including active implementation projects
being worked on. Future work on the transcendental functions and how it
relates to those will be proposed.
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02/07
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Yoo-Ah Kim
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Channel Assignment in Multi-radio Wireless Networks
Abstract: In wireless networks, due to
the broadcast property of the
medium, nearby links may interfere with each other and cannot be used
simultaneously over the same wireless channel. One way to overcome this
limitation is to assign different channels available in the system to
those links. Given a network graph G = (V, E), we consider the problem to
assign channels to links so that we can minimize the total number of
conflicts while satisfying constraints on the number of channels available
at each node and in the entire system. We present simple greedy algorithms
and prove that the algorithms achieve a best possible approximation ratio
under simplified assumptions. We also present a semidefinite programming
(SDP) formulation for the problem which provides a lowerbound on the
optimal solution in general settings. We develop two rounding algorithms
based on the optimal solution to SDP, and show that they achieve a
constant-factor approximation under simplified scenarios. We conduct
experimental evaluations of these algorithms and validate the performance
of our algorithms in various settings.
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02/21
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Hai Lin
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Utilizing Custom Registers in Application-specific
Instruction Set Processors for Register Spills Elimination
Abstract:
Application-specific instruction set processor (ASIP) has become
an important design choice for embedded systems. It can achieve
both high flexibility offered by the base processor core and high
performance and energy efficiency offered by the dedicated hardware
extensions. Although a lot of efforts have been devoted to
computation acceleration, e.g., automatic custom instruction identification
and synthesis, the limited on-chip data storage elements,
including the register file and data cache, have become a potential
performance bottleneck. In this paper, we propose a hardware/
software cooperative approach and a linear scan register allocation
algorithm to utilize the existing custom registers in ASIPs
for eliminating register spills. The data traffic between the processor
and memory can be reduced through efficient on-chip communications
between the base processor core and custom hardware
extensions. Our experimental results demonstrate that a promising
performance gain can be achieved, which is orthogonal to improvements
by any other technique in ASIP design.
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03/14
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Hai Yan
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Abstract:
Random access memory (RAM) is tightly-constrained in many
embedded systems. This is especially true for the least expensive,
lowest-power embedded systems, such as sensor network
nodes and portable consumer electronics. The most widelyused
sensor network nodes have only 4Ð10KB of RAM and
do not contain memory management units (MMUs). It is very
difficult to implement increasingly complex applications under
such tight memory constraints. Nonetheless, price and power
consumption constraints make it unlikely that increases in RAM
in these systems will keep pace with the requirements of applications.
In this presentation, we will introduce several approaches to attack
this problem.
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03/28
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T. Ajithkumar
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Abstract:
FPGA technology has become widely used for real-time packet
classification and data processing. A
library of layered protocol wrappers processes
Internet packets in reconfigurable hardware. The library synthesizes
into field-programmable gate array (FPGA) logic and is utilized in a
network platform called the field-programmable port extender
(FPX).Since the traffic through the network can increase to few Gbps
conventional software systems can not do the real time
processing. The implementation results using FPGA shows that
it can be used for the real time processing. Implementation
of a Content scanning module and a packet classification
architecture (BV-TCAM) it taken to verify this concept.
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