Event Scheduled for Jan 25, 2012
Event: ECE Seminar 'Energy-efficient Instruction Latency Tolerance In 1000-core Data Parallel Processors', Neal Crago, University of Illinois Urbana-Champaign
Location: ITEB 336- Reception begins at 10:30 am
Time: 11:00 am
Details of Event:
Abstract: Power limitations have all but ended single core performance scaling, resulting in computer architects leveraging multiple processor cores on a single die to provide continued performance gains. While there are questions in the software community about developing applications for these parallel processors, another growing realization is that the architectural shift to multi- and many-core has not solved the energy problem. Considering that reducing energy consumption has become even more important as computing has moved towards mobile devices and cloud computing, the shift towards many-core computing requires a rethink in design of future processors.
In this talk, Mr. Crago will discuss his work on solving the energy efficiency problem in the context of 1000-core data parallel processors and future GPUs, by focusing on instruction latency tolerance which is necessary for achieving high-performance. After performing a comprehensive design space exploration on four popular techniques utilizing physical design and performance models, decoupled architectures emerge as an important energy efficiency technique for future many-core chips. He will present OUTRIDER, a novel decoupled architecture that leverages the compiler and is specifically designed to avoid performance and energy pitfalls. The main concept behind OUTRIDER is that through leveraging natural instruction decoupling found in data parallel applications, a serial thread of execution can be partitioned by the compiler into multiple concurrently executing instruction streams providing energy-efficient latency tolerance. The resulting architecture has complexity similar to in-order execution with performance similar to out-of-order execution, while improving energy efficiency significantly over contemporary latency tolerance techniques.
Bio: Neal Crago is a Ph.D. Candidate in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign, and also received his M.S. and B.S. with Honors in ECE from UIUC. His research interests lie in the area of computer architecture and improving the performance, programmability, and energy-efficiency in future many-core computing systems. He is particularly interested in compiler-hardware interactions and designing programmer-friendly parallel processors. He is a student member of IEEE and ACM.
Target Audience: Open to All
Sponsored By: Electrical and Computer Engineering
No Pamphlet/Flyer Available