Event Scheduled for Feb 11, 2013
Event: ECE Faculty Candidate Seminar-Jinghong Chen, South Methodist University- Designing Mixed-Signal and RF/mm-Wave Circuits and Systems for Wireless and Wireline Communications- Reception begins at 12:30 pm
Location: ITEB 336
Time: 01:00 pm
Details of Event:
Abstract:The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for next generation serial link transceivers which must meet tighter performance specifications with a constrained power budget. In the first part of the presentation, I will present an energy-efficient 40 Gb/s optical data link. The data link utilizes a bandwidth efficient sub-carrier modulation scheme with each carrier employing a QAM-16 signaling to reduce the electrical bandwidth and the symbol-rate per channel requirements, allowing low-power and cost-effective CMOS technologies to be used. An integrated QAM-16 transceiver designed in a 0.14μm CMOS technology demonstrated the viability of CMOS technology for implementing ultra wideband optical communication systems. In the first part of the presentation, I will also present a truly-digital reference-less clock-data-recovery (CDR) and digital phased-locked loop circuits for chip-to-chip and backplane I/O communications implemented in a 65nm CMOS technology. The CDR eliminates the large analog capacitor for implementing the phase-locked loop and delay-locked loop and also employs a novel digital scheme where frequency acquisition and phase detection are both performed in lower-speed digital domain, resulting in very low power dissipation and smaller silicon area. The CDR can cover data rates from 1Gb/s to 16 Gb/s, with a JTOL of better than 0.7 UI and RMS jitter of 0.003 UI with a power consumption of less than 5 mW/Gbps.
The recent advances in wireless communications indicate a trend toward integrating multiple communication standards into a single device. Such devices could be implemented with multiple dedicated front-ends integrated in parallel. However, that solution requires larger silicon area and possibly more power consumption. Reconfigurable radio or software-defined ratio transceivers, on the other hand, optimize the functionality versus power and area trade-offs by programming a wideband front-end to the desired standard. In the second part of the presentation, I will first discuss the major system and circuit design challenges for such reconfigurable radio transceivers. I will then present circuit implementations of the major building blocks including a wide-band fractional-N frequency synthesizer and a reconfigurable power-optimized continuous-time sigma-delta modulator supporting the major wireless communication standards including DCS1800, WCDMA, TD-SCDMA, WLAN802.11 a/b/g and Bluetooth. The synthesizer is designed in a 0.13Ám CMOS technology. It occupies an active area of 1.86 mm2 and consumes 35.6 to 52.62 mW of power. Measurement results show that the synthesizer is able to provide in-phase and quadrature-phase (I/Q) signals supporting the standards mentioned above. The sigma-delta data converter is designed in a 1.2V 65nm CMOS process and achieves signal-to-noise-and-distortion-ratio (SNDR) of 73.3/76.5/77.4/ 84.4 dB for 20/10/3/0.5 MHz bandwidth modes with power consumption of 23.9/20.7/9.49/7.22 mW, respectively.
Bio: Jinghong Chen received his Ph.D. in Electrical Engineering from University of Illinois at Urbana-Champaign in 2000. He worked at the High-speed Communication VLSI Research department of Bell Labs, Holmdel/Murray Hill, NJ, from 2001 to 2006 as a Member of Technical Staff. At Bell Labs, he has made a number of contributions on RF and high-speed integrated circuits for different applications, including an ultra-wideband optical communication system, clock-data-recovery and equalization circuits for chip-to-chip and backplane I/O interconnects, a feedback control circuit and system for Lucent Lambda-Router MEMS switching networks, and digital PLL and digital RF transceivers in CMOS and SiGe BiCMOS technologies. From October 2006 to December 2009, he worked at Analog Devices as a Principle Design Engineer and has led a product group developing high-performance CMOS integrated circuits for XM Satellite Radio, multimedia home networking and high-speed SerDes devices. In January 2010, he joined Southern Methodist University in Dallas/TX, as an Associate Professor in Electrical Engineering. His group at SMU (http://lyle.smu.edu/~jhc) is interested in innovating and engineering mixed-signal, RF, and mm-Wave integrated circuits and systems for wireless and wireline communications, senor networks, healthcare, energy harvesting and wireless power, hardware security, and radiation and extreme temperature environment applications. Dr. Chen is a senior member of the IEEE and is currently serving on several conferences Technical Program Committees including IEEE RFIC, EDSSC, RFIT and WAMICON Symposiums and ACM GLSVLSI Symposium. He has published over 60 peer-reviewed conference and journal papers and holds 10 US patents. He is the recipient of the 2012 IEEE WAMICON best paper award.
Target Audience: Open to All
Sponsored By: Electrical and Computer Engineering
No Pamphlet/Flyer Available