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Helena Silva Assistant Professor On faculty since 2006 University of Connecticut Electrical & Computer Engineering 371 Fairfield Way; U-2157 Storrs, CT 06269-2157 USA Office: ITE Building 457 Phone: (860) 486-5517 Fax: (860) 486-2447 E-Mail: hsilva@engr.uconn.edu Personal Page: http://www.engr.uconn.edu/~hsilva

Education:
Ph.D. Applied Physics, Cornell University (2005)
M.S. Applied Physics, Cornell University (2002)
Lic., Engineering Physics, Universidade Tecnica de Lisboa (1998)

Research Interests:
Novel structures and materials for nanoelectronic devices, non-volatile memory devices, electronic transport in the presence of defects and traps, large area electronics, solar cells, sensors, nanofabrication techniques.

Memberships:
American Physical Society (APS)
Institute of Electrical and Electronics Engineers (IEEE)
Materials Research Society (MRS)

Publications

" Random telegraph signal in nano-scale back-side charge trapping memories. " H. Silva and S. Tiwari, Appl. Phys. Lett., 88, 10 (2006).

" Back-side storage non-volatile memories: ultra-thin silicon single crystal silicon layers with complex thin film structure underneath. " H. Silva and S. Tiwari, MRS Fall 2004 Proceedings (2004).

" Nonvolatile silicon memory at the nanoscale. " H. Silva, M. K. Kim, U. Avci, A. Kumar and S. Tiwari, MRS Bulletin, November 2004 (2004).

" A nano-scale memory and transistor based on back-side trapping. " H. Silva and S. Tiwari, IEEE Transactions on Nanotechnology, v 3, 2, p. 264 - 269 (2004).

" Ultra-short SONOS memories. " M. K. Kim, S. D. Chae, H. S. Chae, J. H. Kim, Y. S. Jeong, H. Silva, S. Tiwari, IEEE Transactions on Nanotechnology, v 3, 4, 417- 424 (2004).

" Few electron memories: finding the compromise between performance, variability and manufacturability at the nano-scale. " H. Silva, M. K. Kim, A. Kumar, U. Avci and S. Tiwari, IEDM 2003 Technical Digest p. 271-274 (2003).

" Scaled front-side and back-side SONOS memories. " H. Silva, M. K. Kim and S. Tiwari, IEEE International SOI Conference Proceedings (2003).

" Write, erase and storage times in nano-crystals memories and the role of interface states. " J. Wahl, H. Silva, A. Gokirmak, A. Kumar, J. J. Welser and S. Tiwari, IEDM 1999 Technical Digest p. 375-378 (1999).

" Ion implantation of microcrystalline silicon for low process temperature top-gate thin film transistors. " V. Chu, H. Silva, L. M. Redondo, C. Jesus, M. F. Silva, J. C. Soares, J. P. Conde, Thin Solid Films, 337, 1, p. 203-207 (1999).

" The effect of hydrogen dilution in hot-wire thin film transistors. " J. P. Conde, H. Silva, V. Chu, Amorphous and Microcrystalline Silicon Technology 1998 Symposium Proceedings (1999).

" Hot-wire amorphous thin film transtors: a comparison between top-gate and bottom-gate structures. " V. Chu, J. Jarego, T. Silva, J. Bernardo, H. Silva, P. Brogueira, J. P. Conde, MRS Spring 1998 Proceedings (1998).

" Amorphous silicon thin film transistors with a hot-wire active layer deposited at a high growth rate. " V. Chu, J. Jarego, H. Silva, M. Boucinha, P. Brogueira, J. P. Conde, Amorphous and Microcrystalline Silicon Technology 1997 Symposium (1997).

" Improved mobility of amorphous silicon thin film transistors deposited by hot-wire chemical vapor deposition on glass substrates. " V. Chu, J. Jarego, H. Silva, T. Silva, M. Reissner, P. Brogueira and J. P. Conde, Appl. Phys. Lett. 70, p. 2714-2716 (1997).