As the years have passed, there has been an increasing need for information storage which has lead to a need in high performance storage systems. Over the past decade or so there has been great development with many computer technologies such as microprocessor speed, LAN bandwidth, and disk capacity. Improvements have been made in this area such as a movement towards network storage. Instead of having data stored across many computers within a company for example, it would be in one network accessible by multiple workstations. This is actually encouraged by IT managers because it makes it easier to manage resources as well as improves security. To further improve access speeds, research is being done into the use of active storage networks in order to get better performance I/O in all applications. An active storage network is a network with intelligence. It has the ability to do processing on the data streaming through it.
In order to implement such a network, low cost XUP2VP boards from Xilinx/Diligent are being used as the basis of the processing element. These boards have on board Ethernet connection as well as SATA interfaces. The on board Ethernet connection has a limited speed of 100 Mbps. To maximize speed, these boards will be connected to one another using ROCKET I/O gigabit transceivers which are configured with SATA (Serial Advanced Technology Attachment) interfaces; these have a speed of at least 1Gbps. However, an interface is needed for the endpoints which are connected to the gigabit Ethernet. This interface is the goal of the project.
This interface will be between the Gigabit Ethernet (GigE) RJ45 interface and the SATA interface. This interface will basically make the data received from the RJ45 interface compatible with the SATA interface. A known constraint is that the protocol that ethernet uses is not compatible with SATA. As such the interface will need to take care of this issue. The GigE will require a Physical interface and a MAC (Media Access Control) MAC cannot implement using an FPGA (Field Programmable Logic Array).
The limitations of this project are, to have at least a transfer rate of 1GB/s. The boards should be able to operate at or around 25 degrees Celsius; this is what the temperature will be in/around workstations and computers. For the physical attributes of the project there is no weight restriction but there is a size limitation of 25 square inches or less. Moreover, the data received from RJ45 must be compatible with SATA, and the interface should be well-suited for the network storage for which it was designed.