Project Proposal

As the years have passed, there has been an increasing need for information storage which has lead to a need in high performance storage systems. Over the past decade or so there has been great development with many computer technologies such as microprocessor speed, LAN bandwidth, and disk capacity. One field that has not kept up with this is data access times. Improvements that have been made in this area are a movement towards network storage. Instead of having data stored across many computers within a company for example, it would be in one network accessible by multiple workstations. This is actually encouraged by IT managers because it makes it easier to manage resources as well as improves security. To further improve access speeds, research is being done into the use of active storage networks in order to get better performance I/O in all applications. An active storage network is a network with intelligence. It has the ability to do processing on the data streaming through it. A storage network is being built which requires a transfer rate of 1000Mbps. Our particular project is to create a board that fills in the hole from SATA to this GigEthernet which is required.

This interface will be between the Gigabit Ethernet (GigE) RJ45 interface and the SATA interface found on the XUP2VP board. This interface will make the data received from the RJ45 interface compatible with the SATA interface and vice versa. A known constraint is that the protocol that the RJ45 uses is not compatible with SATA. As such the interface will need to take care of this issue.

The storage network being built will be using a Benes Network. A Benes network is a type of multistage switching network. The advantage of the Benes network as a choice for an ASN (Active Storage Network) switch is that it allows streams of data from multiple source nodes to flow in a hierarchical tree fashion to the single destination node, thus allowing intermediate switch points to perform transformations or reductions on the stream data. The tree based structure also makes broadcasts and scatters easy to implement. In our particular case the XUP2VP board will used as the nodes of the network. Below a diagram of a Benes Network can be found.

There are very few limitations for our project/board. The limitations of this project are that it will be necessary to have a transfer rate of at least 1GB/s. Another limitation is that the boards should be able to operate at or around 25 degrees Celsius; this is what the temperature will be in/around workstations and computers. For the physical attributes of the project there is no weight restriction but there is a size limitation of 25 square inches or less. Moreover, the data received from Ethernet (RJ45) must be compatible with SATA, and the interface should be well-suited for the network storage for which it was designed.

To aid the technical discussion of the GigE interface board project, it has been divided into three major parts which are SATA, Ethernet and Glue Logic.

The first section to be discussed is SATA also known as Serial ATA. Serial ATA is an evolutionary replacement for the Parallel ATA physical storage interface. SATA is a computer bus technology primarily designed for transfer of data to and from a hard disk. This older technology was retroactively renamed Parallel ATA (PATA) to distinguish it from Serial ATA. Both SATA and PATA drives are IDE (Integrated Drive Electronics) drives, although IDE is often misused to indicate PATA drives. SATA uses a 7 wire interface. Three of the wires are ground signals. The other 4 are two pairs of differential signals - one pair in each direction.Advantages of switching to SATA from Parallel ATA are as follows:

Only four of the available eight channels are used on the XUP Virtex-II Pro Development System. Three channels are equipped with low-costs Serial Advanced Technology Attachment (SATA) connectors and the fourth channel terminates at user-supplied Sub-Miniature A (SMA) connectors. The SATA channels are split into two interface formats, two HOST ports ,and a TARGET port. The SATA data rate is less than 2.5 Gb/s so the 75 MHz clocks could have been supplied in the REFCLK inputs.

The SATA Frame structure used between Host and Device is shown in the graphic below. The frame is made up of multi Dwords, which are in turn encapsulated by flow control and CRC information. The SATA frame begins with a Start-of-frame [SOF]. The SOF is followed by the Frame Information Structure [FIS]. Then the Cyclic Redundancy Code [CRC] is placed in the frame. The final block in the message is an End-of-Frame [EOF]. SATA uses a 32bit CRC [calculated over the contents of a (FIS) Frame Information Structure], stored as the 'Dword'. The 32-bit CRC polynomial is X32+ X26+ X23+ X22+ X16+ X12+ X11+ X10+ X8+ X7+ X5+ X4+ X2+ X + 1. Serial ATA is a full duplex protocol. There is a continuous flow of signals from each device moving down the bus.

The second section to be discussed is Ethernet. Ethernet is comprised of Media Access Controllers and a Physical Layer. The Media Access Control sub layer is one of two sub layers that make up the Data Link Layer of the Open Systems Interconnection Model. The OSI Model divides the functions of computer networking intro a series of seven layers. The MAC layer acts as an interface between the Logic Link Control sub layer and the network’s physical layer. Its primary concern is with the control of access to the physical transmission medium. The MAC regulates how a computer gains access to the data and is involved with granting permission to transmit that data.

The MAC moves data packets to and from one network interface card to another. In our particular project the network interface card we are using is the Xilinx XUP-V2Pro. Media Access Controllers have a specific way that data is encapsulated when moving through. Data in the MAC is encapsulated with a 14 byte header in front and a 4 bit Cyclic Redundancy Check after. The 14 byte header consists of three parts. The first part is a 6 byte Destination Address which tells whether the data is being sent to one or multiple computers. The second part is a 6 byte Source Address which tells where the data is coming from. The last part is a 2 bit type field which tells what type of protocol is being used.

For our Gig Ethernet Board a major decision is to decide what we will use for the Media Access sub layer. We narrowed the decision down to three choices; the Intel 82547, the PMC 3386, or build one ourselves. The Intel 82547 is a MAC with an integrated PHY, this chip uses a CSA bus protocol to get data onto the chip. The PMC 3386 does not contain an integrated PHY, therefore it would be necessary to get a separate PHY chip which uses the industry standard GMII protocol. The company Alaska produces many PHY chips that would work with the PMC. Another difference between this chip and the Intel 82547 is that the PMC contains dual Gig Ethernet MACs which would be beneficial because our board is being connected to two Ethernet lines. The last option is to build the MAC ourselves and input it onto the FPGA along with the glue logic. On the website www.opencores.org there is code for a Gig Ethernet MAC. We could implement this on the FPGA and then we would need a separate PHY which would also use the industry standard GMII protocol. We believe the most efficient and best choice is to implement the Gig Ethernet MAC code onto the FPGA and then get a separate PHY.

The third and most intensive part of the GigE Ethernet board is the Glue logic. The purpose of the glue logic is to accepts data packets from the MAC that connects to the gigabit Ethernet and make it compatible with SATA which is used by the XUP 2V - Pro board and vice versa (MAC ↔ SATA).

Discrete Logic:
Team 8 will not be using discrete logic to implement the glue logic for a variety of reasons.

Delay: - Each chip has its own propagation delay, the accumulation delay will be difficult to calculate and manage.
Debugging: - As errors are bound to occur in the design process, debugging is very important. However, this will become increasingly cumbersome as we will need to check the inputs and outputs of each individual chip to find any errors.
Cost: - Individually, the cost of chips are inexpensive. However with the amount of chips that will be required to implement the glue logic, the overall cost can quickly become more exorbitant.
Reliability: - If the glue logic is implemented in discrete logic, problems such as a chip burning out might occur. If this should occur, the current user will have to peruse through our design notes as well as invest a lot of time checking the inputs and outputs of the chips to find the problem and perhaps even more time correcting it.
Upgrades: - If additional functionality is needed in the future, a different system will need to be developed because our system will provide no room for scalability.

The other option is to implement the glue logic using a Field programmable Gate Array. A Field programmable Gate Array is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components also include memory elements, which may be simple flip-flop or more complete blocks of memories.
A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. These logic blocks and interconnects can be programmed after the manufacturing process by the customer/designer (hence the term "field programmable") so that the FPGA can perform whatever logical function is needed (wiki).

Delay: - With the use of a FPGA, there will be only one chip and one propagation delay. This makes the propagation delay easy to calculate and manage.
Debugging: - is a lot easier and more time conservative with a FPGA. All of the errors will probably be software errors, which can be easily found using proper programming techniques.
Cost: - There is only the initial cost of the FPGA, nothing more. The software need to program the FPGA can be gotten online from websites such as www.opencores.org or written by the team. Also, by using an opencores’ version of the MAC, the cost of a MAC will be eliminated.
Reliability: - With the use of a FPGA, the system will be more reliable. If problems should occur after the system has been fully designed and tested, the current user can just reprogram the FPGA with the software program that will be provided by the team. This is a lot less time consuming and easier than the discrete logic option.
Upgrades: - When the need for additional functionality arises, the user can just include the functionality in the software program and reprogram the FPGA. The FPGA’s ability to be reprogrammed makes our system very scalable.

Team 8 will be using an FPGA to implement the glue logic because of the limitations that discrete logic possesses.

There are three major concerns that need to be dealt with to fulfill the objective of the glue logic. These concerns are:

Data format: when data packets are received from the gigabit Ethernet, the useful data will be extracted from the MAC data format and placed into the SATA data format. Using the diagrams below, the useful data will be extracted from the DATA section of the MAC data packet. The data will then be placed into the FIS (Frame Information Structure) of the SATA data frame. The content of the data will not be changed at all during the process of transfer. The CRC (Cyclic Redundancy Code) checksum of the SATA data frame will also be generated by the glue logic. This can be easily achieved by adding all the MAC data words together. The sum of the words will be the CRC checksum for the SATA frame.

When data packets are received from the XUP 2V - Pro board through the SATA port, the data will be extracted from the SATA data format, modified and placed into the MAC data format. Using the diagrams once again, the useful data will be extracted from the FIS of the SATA data frame. This data will then be placed into the DATA section of the MAC data packet. Once again, the content of the data will remain unchanged. The remaining sections of the MAC data packet such as the destination MAC Address, source MAC address, Ethernet type and CRC checksum will also be given in the data packets received from the board. As such, the glue logic will only have to place the right information into the right section.

Error Checking: - Since corrupted or invalid data is of no use to the user. The glue logic will have to check the data packets from the MAC or the XUP 2V - Pro board for errors. This will be accomplished by using the CRC checksums. The glue logic will check any data packet it receives for errors; if the data is corrupted, it will ask for the data packet to be retransmitted. Also, the glue logic will have to generate the CRC checksum for any data packet going to the XUP 2V - Pro board.

Data Transfer Rate: - The data transfer rate of SATA and Ethernet is different; therefore we cannot transfer data directly. The SATA that the XUP 2V - Pro board uses transfers data at the rate less than 2.5 gigabit per second. The Ethernet transfers data at a steady rate of 1 gigabit per second. Also the Ethernet has a clock rate of 1.25 gigahertz. Furthermore, SATA transmit data serially while the MAC transmits data in parallel. For the MAC, the word length will either be 16 or 8 bits. This problem will be solved with the use of clocks, buffers and SERDES (Serializer/Deserializer).

The GigE Interface board project is being sponsored by the Electrical and Computer Department of the University of Connecticut. A limited budget of 1000 dollars has been given to Team 8 to design and implement the Gigabit Ethernet Interface Board. Below is team 8’s estimated budget.

The Gigabit Ethernet board will be used with the Benes Network after it has been implemented. This will enable the ASN to function at Gigabit speeds rather than Megabit speeds. Future work can be done on the Interface to increase its speed from 1 Gigabit per second to 10 or 100 Gigabits per second. The development and implementation of this Interface will allow the user to be able to use low cost XUP 2V - Pro boards as nodes in the ASN rather than buying more expensive boards to use as the nodes. This will hopefully make the development, implementation and maintenance of the Benes Network more cost effective.