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2nd IEEE International Workshop on Hardware-Oriented Security and Trust
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HOST-2009 |
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Monday July 27, 2009
Moscone (will be held in conjunction with DAC-2009)
Submission Deadline (Extended): April 24, 2009 (Click Here for submission) Notification Deadline: June 10, 2009 *new
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You
can register only for HOST if you don’t plan to attend DAC. Early
Registration (Before June 29): Student Member (IEEE or ACM) $150 Member (IEEE or ACM) $200 Non-member $250
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The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust (HOST) issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g., to act as a `kill switch' to disable a chip, to integrated circuit (IC) piracy, to attacks designed to extract encryption keys and IP from a chip, and to malicious system disruption and diversion. HOST covers security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems. The mission of HOST is to provide a forum for the presentation and discussion of research that is of critical significance to the security of, and trust in, modern society's microelectronic-supported infrastructures.
The IEEE International Workshop on Hardware-Oriented Security and Trust (HOST 2009) is an open forum for discussions and innovations on all issues related to hardware security and trust. Paper presentations on topics given below will highlight the challenges faced with authenticating hardware for security and trust. |
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Trojan
detection and isolation
Authenticating
foundry of origin Side
channel analysis/attacks Watermarking IP
security/FPGA design security Cryptographic techniques for hardware security IC Metering |
Physical
unclonable functions (PUFs) Embedded
and distributed systems security Hardware
intrusion detection and prevention Security
engineering Scan-chain encryption IP trust
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To present at the workshop, submit an Acrobat (PDF) version of a paper or extended abstract of at least 1000 words online via EasyChair webpage (clock HERE). The maximum page limit is 8, double column, IEEE format (11 minimum font size). Each submission should include full name and address of each author, affiliation, telephone number, FAX and E-mail address. The accepted papers will appear in ieeexplore. The presenter should also be identified. Camera-ready papers for inclusion in the digest of papers will be due following the review cycle. Proposal for Embedded Tutorials, Debates, Panel Discussions or “Spot-Light” presentations describing industrial experiences are also invited. |
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AUTHOR'S SCHEDULE: Submission of
Paper/Extended Abstract: April
24, 2009 Notification of Acceptance: June 10, 2009 Camera Ready Paper: June 19, 2009 |
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Technical Program Jim
Plusquellic
Electrical and Computer Engineering University of New Mexico Tel:
505-277-0785, x-1439 (FAX) E-mail: jimp@ece.unm.edu
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General
Information Mohammad
Tehranipoor Electrical
and Computer Engineering Tel:
(860) 486-3471, x-2447 (FAX) Email: tehrani@engr.uconn.edu
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